Lines Matching refs:host_int_mask

1364 		orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */  in arcmsr_disable_outbound_ints()
1365 		writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);  in arcmsr_disable_outbound_ints()
1377 		orig_mask = readl(&reg->host_int_mask);  in arcmsr_disable_outbound_ints()
1378 …k | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, &reg->host_int_mask);  in arcmsr_disable_outbound_ints()
1379 		readl(&reg->host_int_mask); /* Dummy readl to force pci flush */  in arcmsr_disable_outbound_ints()
1766 		writel(intmask_org & mask, &reg->host_int_mask);  in arcmsr_enable_outbound_ints()
1782 		writel(intmask_org & mask, &reg->host_int_mask);  in arcmsr_enable_outbound_ints()
3360 	intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */  in arcmsr_hbaC_get_config()
3361 	writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);  in arcmsr_hbaC_get_config()
3405 	intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */  in arcmsr_hbaE_get_config()
3406 	writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);  in arcmsr_hbaE_get_config()
3431 	intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */  in arcmsr_hbaF_get_config()
3432 	writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);  in arcmsr_hbaF_get_config()