216 		if ((NCR5380_read(reg1) & bit1) == val1)  in NCR5380_poll_politely2()
218 		if ((NCR5380_read(reg2) & bit2) == val2)  in NCR5380_poll_politely2()
229 		if ((NCR5380_read(reg1) & bit1) == val1)  in NCR5380_poll_politely2()
231 		if ((NCR5380_read(reg2) & bit2) == val2)  in NCR5380_poll_politely2()
299 	status = NCR5380_read(STATUS_REG);  in NCR5380_print()
300 	mr = NCR5380_read(MODE_REG);  in NCR5380_print()
301 	icr = NCR5380_read(INITIATOR_COMMAND_REG);  in NCR5380_print()
302 	basr = NCR5380_read(BUS_AND_STATUS_REG);  in NCR5380_print()
349 	status = NCR5380_read(STATUS_REG);  in NCR5380_print_phase()
446 		NCR5380_read(STATUS_REG);  in NCR5380_init()
475 	for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) {  in NCR5380_maybe_reset_bus()
768 			if ((NCR5380_read(BUS_AND_STATUS_REG) &  in NCR5380_dma_complete()
771 				saved_data = NCR5380_read(INPUT_DATA_REG);  in NCR5380_dma_complete()
785 	if ((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | BASR_ACK)) ==  in NCR5380_dma_complete()
788 		       NCR5380_read(BUS_AND_STATUS_REG));  in NCR5380_dma_complete()
797 	NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_dma_complete()
810 		if ((NCR5380_read(STATUS_REG) & PHASE_MASK) == p && (p & SR_IO)) {  in NCR5380_dma_complete()
874 	basr = NCR5380_read(BUS_AND_STATUS_REG);  in NCR5380_intr()
876 		unsigned char mr = NCR5380_read(MODE_REG);  in NCR5380_intr()
877 		unsigned char sr = NCR5380_read(STATUS_REG);  in NCR5380_intr()
895 				NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_intr()
897 		} else if ((NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_mask) &&  in NCR5380_intr()
901 			NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_intr()
913 			NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_intr()
1014 	if (!(NCR5380_read(MODE_REG) & MR_ARBITRATE)) {  in NCR5380_select()
1035 	if ((NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) ||  in NCR5380_select()
1036 	    (NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_higher_mask) ||  in NCR5380_select()
1037 	    (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST)) {  in NCR5380_select()
1064 	if (!(NCR5380_read(MODE_REG) & MR_ARBITRATE))  in NCR5380_select()
1139 	if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) {  in NCR5380_select()
1287 		if ((NCR5380_read(STATUS_REG) & PHASE_MASK) != p) {  in NCR5380_transfer_pio()
1297 			*d = NCR5380_read(CURRENT_SCSI_DATA_REG);  in NCR5380_transfer_pio()
1355 	tmp = NCR5380_read(STATUS_REG);  in NCR5380_transfer_pio()
1390 	              PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));  in do_reset()
1394 	(void)NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in do_reset()
1432 	tmp = NCR5380_read(STATUS_REG) & PHASE_MASK;  in do_abort()
1494 	if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) {  in NCR5380_transfer_dma()
1638 			d[*count - 1] = NCR5380_read(INPUT_DATA_REG);  in NCR5380_transfer_dma()
1693 		tmp = NCR5380_read(STATUS_REG);  in NCR5380_information_transfer()
1730 				while (NCR5380_read(STATUS_REG) & SR_REQ)  in NCR5380_information_transfer()
2041 	target_mask = NCR5380_read(CURRENT_SCSI_DATA_REG) & ~(hostdata->id_mask);  in NCR5380_reselect()
2072 		if ((NCR5380_read(STATUS_REG) & (SR_BSY | SR_SEL)) == 0)  in NCR5380_reselect()
2085 	msg[0] = NCR5380_read(CURRENT_SCSI_DATA_REG);  in NCR5380_reselect()