Lines Matching +full:0 +full:x00d00000
62 [0x000] = "INFO: AEN queue empty",
63 [0x001] = "INFO: Soft reset occurred",
64 [0x002] = "ERROR: Unit degraded: Unit #",
65 [0x003] = "ERROR: Controller error",
66 [0x004] = "ERROR: Rebuild failed: Unit #",
67 [0x005] = "INFO: Rebuild complete: Unit #",
68 [0x006] = "ERROR: Incomplete unit detected: Unit #",
69 [0x007] = "INFO: Initialization complete: Unit #",
70 [0x008] = "WARNING: Unclean shutdown detected: Unit #",
71 [0x009] = "WARNING: ATA port timeout: Port #",
72 [0x00A] = "ERROR: Drive error: Port #",
73 [0x00B] = "INFO: Rebuild started: Unit #",
74 [0x00C] = "INFO: Initialization started: Unit #",
75 [0x00D] = "ERROR: Logical unit deleted: Unit #",
76 [0x00F] = "WARNING: SMART threshold exceeded: Port #",
77 [0x021] = "WARNING: ATA UDMA downgrade: Port #",
78 [0x022] = "WARNING: ATA UDMA upgrade: Port #",
79 [0x023] = "WARNING: Sector repair occurred: Port #",
80 [0x024] = "ERROR: SBUF integrity check failure",
81 [0x025] = "ERROR: Lost cached write: Port #",
82 [0x026] = "ERROR: Drive ECC error detected: Port #",
83 [0x027] = "ERROR: DCB checksum error: Port #",
84 [0x028] = "ERROR: DCB unsupported version: Port #",
85 [0x029] = "INFO: Verify started: Unit #",
86 [0x02A] = "ERROR: Verify failed: Port #",
87 [0x02B] = "INFO: Verify complete: Unit #",
88 [0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #",
89 [0x02D] = "ERROR: Encountered bad sector during rebuild: Port #",
90 [0x02E] = "ERROR: Replacement drive is too small: Port #",
91 [0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #",
92 [0x030] = "ERROR: Drive not supported: Port #"
103 {0x01, 0x03, 0x13, 0x00}, // Address mark not found Address mark not found for data field
104 {0x04, 0x0b, 0x00, 0x00}, // Aborted command Aborted command
105 {0x10, 0x0b, 0x14, 0x00}, // ID not found Recorded entity not found
106 {0x40, 0x03, 0x11, 0x00}, // Uncorrectable ECC error Unrecovered read error
107 {0x61, 0x04, 0x00, 0x00}, // Device fault Hardware error
108 {0x84, 0x0b, 0x47, 0x00}, // Data CRC error SCSI parity error
109 {0xd0, 0x0b, 0x00, 0x00}, // Device busy Aborted command
110 {0xd1, 0x0b, 0x00, 0x00}, // Device busy Aborted command
111 {0x37, 0x02, 0x04, 0x00}, // Unit offline Not ready
112 {0x09, 0x02, 0x04, 0x00}, // Unrecovered disk error Not ready
116 {0x51, 0x0b, 0x00, 0x00} // Unspecified Aborted command
120 #define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
121 #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
122 #define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
123 #define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
124 #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
125 #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
126 #define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200
127 #define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100
128 #define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080
129 #define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040
130 #define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
131 #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
132 #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
133 #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
134 #define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008
137 #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
138 #define TW_STATUS_MINOR_VERSION_MASK 0x0F000000
139 #define TW_STATUS_PCI_PARITY_ERROR 0x00800000
140 #define TW_STATUS_QUEUE_ERROR 0x00400000
141 #define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000
142 #define TW_STATUS_PCI_ABORT 0x00100000
143 #define TW_STATUS_HOST_INTERRUPT 0x00080000
144 #define TW_STATUS_ATTENTION_INTERRUPT 0x00040000
145 #define TW_STATUS_COMMAND_INTERRUPT 0x00020000
146 #define TW_STATUS_RESPONSE_INTERRUPT 0x00010000
147 #define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000
148 #define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
149 #define TW_STATUS_MICROCONTROLLER_READY 0x00002000
150 #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
151 #define TW_STATUS_ALL_INTERRUPTS 0x000F0000
152 #define TW_STATUS_CLEARABLE_BITS 0x00D00000
153 #define TW_STATUS_EXPECTED_BITS 0x00002000
154 #define TW_STATUS_UNEXPECTED_BITS 0x00F00008
155 #define TW_STATUS_SBUF_WRITE_ERROR 0x00000008
156 #define TW_STATUS_VALID_INTERRUPT 0x00DF0008
159 #define TW_RESPONSE_ID_MASK 0x00000FF0
162 #define TW_IO_ADDRESS_RANGE 0x10
164 #define TW_VENDOR_ID (0x13C1) /* 3ware */
165 #define TW_DEVICE_ID (0x1000) /* Storage Controller */
166 #define TW_DEVICE_ID2 (0x1001) /* 7000 series controller */
168 #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
169 #define TW_PCI_CLEAR_PCI_ABORT 0x2000
172 #define TW_OP_NOP 0x0
173 #define TW_OP_INIT_CONNECTION 0x1
174 #define TW_OP_READ 0x2
175 #define TW_OP_WRITE 0x3
176 #define TW_OP_VERIFY 0x4
177 #define TW_OP_GET_PARAM 0x12
178 #define TW_OP_SET_PARAM 0x13
179 #define TW_OP_SECTOR_INFO 0x1a
180 #define TW_OP_AEN_LISTEN 0x1c
181 #define TW_OP_FLUSH_CACHE 0x0e
182 #define TW_CMD_PACKET 0x1d
183 #define TW_CMD_PACKET_WITH_DATA 0x1f
186 #define TW_AEN_QUEUE_EMPTY 0x0000
187 #define TW_AEN_SOFT_RESET 0x0001
188 #define TW_AEN_DEGRADED_MIRROR 0x0002
189 #define TW_AEN_CONTROLLER_ERROR 0x0003
190 #define TW_AEN_REBUILD_FAIL 0x0004
191 #define TW_AEN_REBUILD_DONE 0x0005
192 #define TW_AEN_QUEUE_FULL 0x00ff
193 #define TW_AEN_TABLE_UNDEFINED 0x15
194 #define TW_AEN_APORT_TIMEOUT 0x0009
195 #define TW_AEN_DRIVE_ERROR 0x000A
196 #define TW_AEN_SMART_FAIL 0x000F
197 #define TW_AEN_SBUF_FAIL 0x0024
203 #define TW_COMMAND_ALIGNMENT_MASK 0x1ff
204 #define TW_INIT_MESSAGE_CREDITS 0x100
205 #define TW_INIT_COMMAND_PACKET_SIZE 0x3
210 #define TW_Q_START 0
214 #define TW_UNIT_INFORMATION_TABLE_BASE 0x300
218 #define TW_BLOCK_SIZE 0x200 /* 512-byte blocks */
219 #define TW_IOCTL 0x80
238 #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
239 #define TW_SGL_OUT(x) ((x >> 5) & 0x7)
242 #define TW_RESID_OUT(x) ((x >> 4) & 0xff)
245 #define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
246 #define TW_UNIT_OUT(x) (x & 0xf)
250 #define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
251 #define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
252 #define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
286 #define dprintk(msg...) do { } while(0)
370 #define TW_S_INITIAL 0x1 /* Initial state */
371 #define TW_S_STARTED 0x2 /* Id in use */
372 #define TW_S_POSTED 0x4 /* Posted to the controller */
373 #define TW_S_PENDING 0x8 /* Waiting to be posted in isr */
374 #define TW_S_COMPLETED 0x10 /* Completed by isr */
375 #define TW_S_FINISHED 0x20 /* I/O completely done */