1 // SPDX-License-Identifier: GPL-2.0+
3  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
66 	return readl(rtc->base + reg);  in jz4740_rtc_reg_read()
72 	int timeout = 10000;  in jz4740_rtc_wait_write_ready()  local
76 	} while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);  in jz4740_rtc_wait_write_ready()
78 	return timeout ? 0 : -EIO;  in jz4740_rtc_wait_write_ready()
84 	int ret, timeout = 10000;  in jz4780_rtc_enable_write()  local
90 	writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);  in jz4780_rtc_enable_write()
93 		ctrl = readl(rtc->base + JZ_REG_RTC_WENR);  in jz4780_rtc_enable_write()
94 	} while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);  in jz4780_rtc_enable_write()
96 	return timeout ? 0 : -EIO;  in jz4780_rtc_enable_write()
104 	if (rtc->type >= ID_JZ4760)  in jz4740_rtc_reg_write()
109 		writel(val, rtc->base + reg);  in jz4740_rtc_reg_write()
121 	spin_lock_irqsave(&rtc->lock, flags);  in jz4740_rtc_ctrl_set_bits()
135 	spin_unlock_irqrestore(&rtc->lock, flags);  in jz4740_rtc_ctrl_set_bits()
144 	int timeout = 5;  in jz4740_rtc_read_time()  local
147 		return -EINVAL;  in jz4740_rtc_read_time()
156 	while (secs != secs2 && --timeout) {  in jz4740_rtc_read_time()
161 	if (timeout == 0)  in jz4740_rtc_read_time()
162 		return -EIO;  in jz4740_rtc_read_time()
191 	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);  in jz4740_rtc_read_alarm()
192 	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);  in jz4740_rtc_read_alarm()
194 	rtc_time64_to_tm(secs, &alrm->time);  in jz4740_rtc_read_alarm()
203 	uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));  in jz4740_rtc_set_alarm()
208 			JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);  in jz4740_rtc_set_alarm()
241 	rtc_update_irq(rtc->rtc, 1, events);  in jz4740_rtc_irq()
261 	{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
262 	{ .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
263 	{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
273 	unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */  in jz4740_rtc_set_wakeup_params()
274 	unsigned int reset_pin_assert_time = 100; /* Default: 100ms */  in jz4740_rtc_set_wakeup_params()
276 	of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",  in jz4740_rtc_set_wakeup_params()
278 	of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",  in jz4740_rtc_set_wakeup_params()
282 	 * Set minimum wakeup pin assertion time: 100 ms.  in jz4740_rtc_set_wakeup_params()
293 	 * Set reset pin low-level assertion time after wakeup: 60 ms.  in jz4740_rtc_set_wakeup_params()
294 	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.  in jz4740_rtc_set_wakeup_params()
306 	struct device *dev = &pdev->dev;  in jz4740_rtc_probe()
307 	struct device_node *np = dev->of_node;  in jz4740_rtc_probe()
315 		return -ENOMEM;  in jz4740_rtc_probe()
317 	rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev);  in jz4740_rtc_probe()
323 	rtc->base = devm_platform_ioremap_resource(pdev, 0);  in jz4740_rtc_probe()
324 	if (IS_ERR(rtc->base))  in jz4740_rtc_probe()
325 		return PTR_ERR(rtc->base);  in jz4740_rtc_probe()
331 	spin_lock_init(&rtc->lock);  in jz4740_rtc_probe()
343 	rtc->rtc = devm_rtc_allocate_device(dev);  in jz4740_rtc_probe()
344 	if (IS_ERR(rtc->rtc)) {  in jz4740_rtc_probe()
345 		ret = PTR_ERR(rtc->rtc);  in jz4740_rtc_probe()
350 	rtc->rtc->ops = &jz4740_rtc_ops;  in jz4740_rtc_probe()
351 	rtc->rtc->range_max = U32_MAX;  in jz4740_rtc_probe()
357 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);  in jz4740_rtc_probe()
359 	ret = devm_rtc_register_device(rtc->rtc);  in jz4740_rtc_probe()
364 			       pdev->name, rtc);  in jz4740_rtc_probe()
385 		.name  = "jz4740-rtc",
392 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
395 MODULE_ALIAS("platform:jz4740-rtc");