Lines Matching +full:qcs404 +full:- +full:evb
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Linaro Ltd.
5 * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
161 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
163 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
166 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
168 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
171 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
175 dev_err(wcss->dev, in q6v5_wcss_reset()
180 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
182 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
187 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
190 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
192 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
196 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
199 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
200 for (i = MEM_BANKS; i >= 0; i--) { in q6v5_wcss_reset()
202 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
208 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
212 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
214 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
218 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
221 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
223 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
226 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
228 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
231 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
233 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
240 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_start()
243 qcom_q6v5_prepare(&wcss->q6v5); in q6v5_wcss_start()
246 ret = reset_control_deassert(wcss->wcss_reset); in q6v5_wcss_start()
248 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_wcss_start()
252 ret = reset_control_deassert(wcss->wcss_q6_reset); in q6v5_wcss_start()
254 dev_err(wcss->dev, "wcss_q6_reset failed\n"); in q6v5_wcss_start()
258 /* Lithium configuration - clock gating and bus arbitration */ in q6v5_wcss_start()
259 ret = regmap_update_bits(wcss->halt_map, in q6v5_wcss_start()
260 wcss->halt_nc + TCSR_GLOBAL_CFG0, in q6v5_wcss_start()
266 ret = regmap_update_bits(wcss->halt_map, in q6v5_wcss_start()
267 wcss->halt_nc + TCSR_GLOBAL_CFG1, in q6v5_wcss_start()
272 /* Write bootaddr to EVB so that Q6WCSS will jump there after reset */ in q6v5_wcss_start()
273 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); in q6v5_wcss_start()
279 ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); in q6v5_wcss_start()
280 if (ret == -ETIMEDOUT) in q6v5_wcss_start()
281 dev_err(wcss->dev, "start timed out\n"); in q6v5_wcss_start()
286 reset_control_assert(wcss->wcss_q6_reset); in q6v5_wcss_start()
289 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_start()
300 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_qcs404_power_on()
302 reset_control_deassert(wcss->wcss_reset); in q6v5_wcss_qcs404_power_on()
306 ret = clk_prepare_enable(wcss->gcc_abhs_cbcr); in q6v5_wcss_qcs404_power_on()
311 reset_control_deassert(wcss->wcss_q6_bcr_reset); in q6v5_wcss_qcs404_power_on()
314 ret = clk_prepare_enable(wcss->ahbfabric_cbcr_clk); in q6v5_wcss_qcs404_power_on()
319 ret = clk_prepare_enable(wcss->lcc_csr_cbcr); in q6v5_wcss_qcs404_power_on()
324 ret = clk_prepare_enable(wcss->ahbs_cbcr); in q6v5_wcss_qcs404_power_on()
329 ret = clk_prepare_enable(wcss->tcm_slave_cbcr); in q6v5_wcss_qcs404_power_on()
334 ret = clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr); in q6v5_wcss_qcs404_power_on()
339 ret = clk_prepare_enable(wcss->qdsp6ss_axim_cbcr); in q6v5_wcss_qcs404_power_on()
344 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
346 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
348 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_qcs404_power_on()
352 dev_err(wcss->dev, in q6v5_wcss_qcs404_power_on()
357 writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE); in q6v5_wcss_qcs404_power_on()
360 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
362 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
365 ret = clk_prepare_enable(wcss->gcc_axim_cbcr); in q6v5_wcss_qcs404_power_on()
370 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
372 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
375 writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
377 writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
379 writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
381 writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
385 * bank at a time to avoid in-rush current in q6v5_wcss_qcs404_power_on()
387 for (idx = 28; idx >= 0; idx--) { in q6v5_wcss_qcs404_power_on()
388 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) | in q6v5_wcss_qcs404_power_on()
389 (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_qcs404_power_on()
392 writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
393 writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
395 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
397 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
400 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
402 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
405 ret = clk_prepare_enable(wcss->lcc_bcr_sleep); in q6v5_wcss_qcs404_power_on()
412 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
414 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
415 clk_disable_unprepare(wcss->gcc_axim_cbcr); in q6v5_wcss_qcs404_power_on()
417 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
419 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
420 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
422 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
423 clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); in q6v5_wcss_qcs404_power_on()
425 clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); in q6v5_wcss_qcs404_power_on()
427 clk_disable_unprepare(wcss->tcm_slave_cbcr); in q6v5_wcss_qcs404_power_on()
429 clk_disable_unprepare(wcss->ahbs_cbcr); in q6v5_wcss_qcs404_power_on()
431 clk_disable_unprepare(wcss->lcc_csr_cbcr); in q6v5_wcss_qcs404_power_on()
433 clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); in q6v5_wcss_qcs404_power_on()
435 clk_disable_unprepare(wcss->gcc_abhs_cbcr); in q6v5_wcss_qcs404_power_on()
444 writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC); in q6v5_wcss_qcs404_reset()
447 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_reset()
449 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_reset()
456 struct q6v5_wcss *wcss = rproc->priv; in q6v5_qcs404_wcss_start()
459 ret = clk_prepare_enable(wcss->xo); in q6v5_qcs404_wcss_start()
463 ret = regulator_enable(wcss->cx_supply); in q6v5_qcs404_wcss_start()
467 qcom_q6v5_prepare(&wcss->q6v5); in q6v5_qcs404_wcss_start()
471 dev_err(wcss->dev, "wcss clk_enable failed\n"); in q6v5_qcs404_wcss_start()
475 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); in q6v5_qcs404_wcss_start()
479 ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); in q6v5_qcs404_wcss_start()
480 if (ret == -ETIMEDOUT) { in q6v5_qcs404_wcss_start()
481 dev_err(wcss->dev, "start timed out\n"); in q6v5_qcs404_wcss_start()
488 regulator_disable(wcss->cx_supply); in q6v5_qcs404_wcss_start()
490 clk_disable_unprepare(wcss->xo); in q6v5_qcs404_wcss_start()
523 dev_err(wcss->dev, "port failed halt\n"); in q6v5_wcss_halt_axi_port()
534 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); in q6v5_qcs404_wcss_shutdown()
537 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
539 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
542 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) & in q6v5_qcs404_wcss_shutdown()
544 wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_qcs404_wcss_shutdown()
547 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
549 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
551 clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); in q6v5_qcs404_wcss_shutdown()
552 clk_disable_unprepare(wcss->lcc_csr_cbcr); in q6v5_qcs404_wcss_shutdown()
553 clk_disable_unprepare(wcss->tcm_slave_cbcr); in q6v5_qcs404_wcss_shutdown()
554 clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); in q6v5_qcs404_wcss_shutdown()
555 clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); in q6v5_qcs404_wcss_shutdown()
557 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_qcs404_wcss_shutdown()
559 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_qcs404_wcss_shutdown()
561 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_qcs404_wcss_shutdown()
563 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_qcs404_wcss_shutdown()
565 clk_disable_unprepare(wcss->ahbs_cbcr); in q6v5_qcs404_wcss_shutdown()
566 clk_disable_unprepare(wcss->lcc_bcr_sleep); in q6v5_qcs404_wcss_shutdown()
568 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
570 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
572 clk_disable_unprepare(wcss->gcc_abhs_cbcr); in q6v5_qcs404_wcss_shutdown()
574 ret = reset_control_assert(wcss->wcss_reset); in q6v5_qcs404_wcss_shutdown()
576 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_qcs404_wcss_shutdown()
581 ret = reset_control_deassert(wcss->wcss_reset); in q6v5_qcs404_wcss_shutdown()
583 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_qcs404_wcss_shutdown()
588 clk_disable_unprepare(wcss->gcc_axim_cbcr); in q6v5_qcs404_wcss_shutdown()
598 /* 1 - Assert WCSS/Q6 HALTREQ */ in q6v5_wcss_powerdown()
599 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); in q6v5_wcss_powerdown()
601 /* 2 - Enable WCSSAON_CONFIG */ in q6v5_wcss_powerdown()
602 val = readl(wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
604 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
606 /* 3 - Set SSCAON_CONFIG */ in q6v5_wcss_powerdown()
609 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
611 /* 4 - SSCAON_CONFIG 1 */ in q6v5_wcss_powerdown()
613 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
615 /* 5 - wait for SSCAON_STATUS */ in q6v5_wcss_powerdown()
616 ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS, in q6v5_wcss_powerdown()
620 dev_err(wcss->dev, in q6v5_wcss_powerdown()
625 /* 6 - De-assert WCSS_AON reset */ in q6v5_wcss_powerdown()
626 reset_control_assert(wcss->wcss_aon_reset); in q6v5_wcss_powerdown()
628 /* 7 - Disable WCSSAON_CONFIG 13 */ in q6v5_wcss_powerdown()
629 val = readl(wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
631 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
633 /* 8 - De-assert WCSS/Q6 HALTREQ */ in q6v5_wcss_powerdown()
634 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_powerdown()
645 /* 1 - Halt Q6 bus interface */ in q6v5_q6_powerdown()
646 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6); in q6v5_q6_powerdown()
648 /* 2 - Disable Q6 Core clock */ in q6v5_q6_powerdown()
649 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
651 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
653 /* 3 - Clamp I/O */ in q6v5_q6_powerdown()
654 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
656 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
658 /* 4 - Clamp WL */ in q6v5_q6_powerdown()
660 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
662 /* 5 - Clear Erase standby */ in q6v5_q6_powerdown()
664 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
666 /* 6 - Clear Sleep RTN */ in q6v5_q6_powerdown()
668 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
670 /* 7 - turn off Q6 memory foot/head switch one bank at a time */ in q6v5_q6_powerdown()
672 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
674 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
678 /* 8 - Assert QMC memory RTN */ in q6v5_q6_powerdown()
679 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
681 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
683 /* 9 - Turn off BHS */ in q6v5_q6_powerdown()
685 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
688 /* 10 - Wait till BHS Reset is done */ in q6v5_q6_powerdown()
689 ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS, in q6v5_q6_powerdown()
693 dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret); in q6v5_q6_powerdown()
697 /* 11 - Assert WCSS reset */ in q6v5_q6_powerdown()
698 reset_control_assert(wcss->wcss_reset); in q6v5_q6_powerdown()
700 /* 12 - Assert Q6 reset */ in q6v5_q6_powerdown()
701 reset_control_assert(wcss->wcss_q6_reset); in q6v5_q6_powerdown()
708 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_stop()
712 if (wcss->requires_force_stop) { in q6v5_wcss_stop()
713 ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); in q6v5_wcss_stop()
714 if (ret == -ETIMEDOUT) { in q6v5_wcss_stop()
715 dev_err(wcss->dev, "timed out on wait\n"); in q6v5_wcss_stop()
720 if (wcss->version == WCSS_QCS404) { in q6v5_wcss_stop()
735 qcom_q6v5_unprepare(&wcss->q6v5); in q6v5_wcss_stop()
742 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_da_to_va()
745 offset = da - wcss->mem_reloc; in q6v5_wcss_da_to_va()
746 if (offset < 0 || offset + len > wcss->mem_size) in q6v5_wcss_da_to_va()
749 return wcss->mem_region + offset; in q6v5_wcss_da_to_va()
754 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_load()
757 ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, in q6v5_wcss_load()
758 0, wcss->mem_region, wcss->mem_phys, in q6v5_wcss_load()
759 wcss->mem_size, &wcss->mem_reloc); in q6v5_wcss_load()
763 qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size); in q6v5_wcss_load()
788 struct device *dev = wcss->dev; in q6v5_wcss_init_reset()
790 if (desc->aon_reset_required) { in q6v5_wcss_init_reset()
791 wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset"); in q6v5_wcss_init_reset()
792 if (IS_ERR(wcss->wcss_aon_reset)) { in q6v5_wcss_init_reset()
793 dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n"); in q6v5_wcss_init_reset()
794 return PTR_ERR(wcss->wcss_aon_reset); in q6v5_wcss_init_reset()
798 wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset"); in q6v5_wcss_init_reset()
799 if (IS_ERR(wcss->wcss_reset)) { in q6v5_wcss_init_reset()
800 dev_err(wcss->dev, "unable to acquire wcss_reset\n"); in q6v5_wcss_init_reset()
801 return PTR_ERR(wcss->wcss_reset); in q6v5_wcss_init_reset()
804 if (desc->wcss_q6_reset_required) { in q6v5_wcss_init_reset()
805 wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset"); in q6v5_wcss_init_reset()
806 if (IS_ERR(wcss->wcss_q6_reset)) { in q6v5_wcss_init_reset()
807 dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); in q6v5_wcss_init_reset()
808 return PTR_ERR(wcss->wcss_q6_reset); in q6v5_wcss_init_reset()
812 wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset"); in q6v5_wcss_init_reset()
813 if (IS_ERR(wcss->wcss_q6_bcr_reset)) { in q6v5_wcss_init_reset()
814 dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); in q6v5_wcss_init_reset()
815 return PTR_ERR(wcss->wcss_q6_bcr_reset); in q6v5_wcss_init_reset()
830 wcss->reg_base = devm_ioremap(&pdev->dev, res->start, in q6v5_wcss_init_mmio()
832 if (!wcss->reg_base) in q6v5_wcss_init_mmio()
833 return -ENOMEM; in q6v5_wcss_init_mmio()
835 if (wcss->version == WCSS_IPQ8074) { in q6v5_wcss_init_mmio()
837 wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res); in q6v5_wcss_init_mmio()
838 if (IS_ERR(wcss->rmb_base)) in q6v5_wcss_init_mmio()
839 return PTR_ERR(wcss->rmb_base); in q6v5_wcss_init_mmio()
842 syscon = of_parse_phandle(pdev->dev.of_node, in q6v5_wcss_init_mmio()
843 "qcom,halt-regs", 0); in q6v5_wcss_init_mmio()
845 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); in q6v5_wcss_init_mmio()
846 return -EINVAL; in q6v5_wcss_init_mmio()
849 wcss->halt_map = syscon_node_to_regmap(syscon); in q6v5_wcss_init_mmio()
851 if (IS_ERR(wcss->halt_map)) in q6v5_wcss_init_mmio()
852 return PTR_ERR(wcss->halt_map); in q6v5_wcss_init_mmio()
854 ret = of_property_read_variable_u32_array(pdev->dev.of_node, in q6v5_wcss_init_mmio()
855 "qcom,halt-regs", in q6v5_wcss_init_mmio()
859 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); in q6v5_wcss_init_mmio()
860 return -EINVAL; in q6v5_wcss_init_mmio()
863 wcss->halt_q6 = halt_reg[0]; in q6v5_wcss_init_mmio()
864 wcss->halt_wcss = halt_reg[1]; in q6v5_wcss_init_mmio()
865 wcss->halt_nc = halt_reg[2]; in q6v5_wcss_init_mmio()
874 struct device *dev = wcss->dev; in q6v5_alloc_memory_region()
876 node = of_parse_phandle(dev->of_node, "memory-region", 0); in q6v5_alloc_memory_region()
882 dev_err(dev, "unable to acquire memory-region\n"); in q6v5_alloc_memory_region()
883 return -EINVAL; in q6v5_alloc_memory_region()
886 wcss->mem_phys = rmem->base; in q6v5_alloc_memory_region()
887 wcss->mem_reloc = rmem->base; in q6v5_alloc_memory_region()
888 wcss->mem_size = rmem->size; in q6v5_alloc_memory_region()
889 wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size); in q6v5_alloc_memory_region()
890 if (!wcss->mem_region) { in q6v5_alloc_memory_region()
892 &rmem->base, &rmem->size); in q6v5_alloc_memory_region()
893 return -EBUSY; in q6v5_alloc_memory_region()
903 wcss->xo = devm_clk_get(wcss->dev, "xo"); in q6v5_wcss_init_clock()
904 if (IS_ERR(wcss->xo)) { in q6v5_wcss_init_clock()
905 ret = PTR_ERR(wcss->xo); in q6v5_wcss_init_clock()
906 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
907 dev_err(wcss->dev, "failed to get xo clock"); in q6v5_wcss_init_clock()
911 wcss->gcc_abhs_cbcr = devm_clk_get(wcss->dev, "gcc_abhs_cbcr"); in q6v5_wcss_init_clock()
912 if (IS_ERR(wcss->gcc_abhs_cbcr)) { in q6v5_wcss_init_clock()
913 ret = PTR_ERR(wcss->gcc_abhs_cbcr); in q6v5_wcss_init_clock()
914 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
915 dev_err(wcss->dev, "failed to get gcc abhs clock"); in q6v5_wcss_init_clock()
919 wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr"); in q6v5_wcss_init_clock()
920 if (IS_ERR(wcss->gcc_axim_cbcr)) { in q6v5_wcss_init_clock()
921 ret = PTR_ERR(wcss->gcc_axim_cbcr); in q6v5_wcss_init_clock()
922 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
923 dev_err(wcss->dev, "failed to get gcc axim clock\n"); in q6v5_wcss_init_clock()
927 wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev, in q6v5_wcss_init_clock()
929 if (IS_ERR(wcss->ahbfabric_cbcr_clk)) { in q6v5_wcss_init_clock()
930 ret = PTR_ERR(wcss->ahbfabric_cbcr_clk); in q6v5_wcss_init_clock()
931 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
932 dev_err(wcss->dev, "failed to get ahbfabric clock\n"); in q6v5_wcss_init_clock()
936 wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "tcsr_lcc_cbc"); in q6v5_wcss_init_clock()
937 if (IS_ERR(wcss->lcc_csr_cbcr)) { in q6v5_wcss_init_clock()
938 ret = PTR_ERR(wcss->lcc_csr_cbcr); in q6v5_wcss_init_clock()
939 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
940 dev_err(wcss->dev, "failed to get csr cbcr clk\n"); in q6v5_wcss_init_clock()
944 wcss->ahbs_cbcr = devm_clk_get(wcss->dev, in q6v5_wcss_init_clock()
946 if (IS_ERR(wcss->ahbs_cbcr)) { in q6v5_wcss_init_clock()
947 ret = PTR_ERR(wcss->ahbs_cbcr); in q6v5_wcss_init_clock()
948 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
949 dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n"); in q6v5_wcss_init_clock()
953 wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev, in q6v5_wcss_init_clock()
955 if (IS_ERR(wcss->tcm_slave_cbcr)) { in q6v5_wcss_init_clock()
956 ret = PTR_ERR(wcss->tcm_slave_cbcr); in q6v5_wcss_init_clock()
957 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
958 dev_err(wcss->dev, "failed to get tcm cbcr clk\n"); in q6v5_wcss_init_clock()
962 wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "lcc_abhm_cbc"); in q6v5_wcss_init_clock()
963 if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) { in q6v5_wcss_init_clock()
964 ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr); in q6v5_wcss_init_clock()
965 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
966 dev_err(wcss->dev, "failed to get abhm cbcr clk\n"); in q6v5_wcss_init_clock()
970 wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "lcc_axim_cbc"); in q6v5_wcss_init_clock()
971 if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) { in q6v5_wcss_init_clock()
972 ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr); in q6v5_wcss_init_clock()
973 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
974 dev_err(wcss->dev, "failed to get axim cbcr clk\n"); in q6v5_wcss_init_clock()
978 wcss->lcc_bcr_sleep = devm_clk_get(wcss->dev, "lcc_bcr_sleep"); in q6v5_wcss_init_clock()
979 if (IS_ERR(wcss->lcc_bcr_sleep)) { in q6v5_wcss_init_clock()
980 ret = PTR_ERR(wcss->lcc_bcr_sleep); in q6v5_wcss_init_clock()
981 if (ret != -EPROBE_DEFER) in q6v5_wcss_init_clock()
982 dev_err(wcss->dev, "failed to get bcr cbcr clk\n"); in q6v5_wcss_init_clock()
991 wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); in q6v5_wcss_init_regulator()
992 if (IS_ERR(wcss->cx_supply)) in q6v5_wcss_init_regulator()
993 return PTR_ERR(wcss->cx_supply); in q6v5_wcss_init_regulator()
995 regulator_set_load(wcss->cx_supply, 100000); in q6v5_wcss_init_regulator()
1007 desc = device_get_match_data(&pdev->dev); in q6v5_wcss_probe()
1009 return -EINVAL; in q6v5_wcss_probe()
1011 rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, in q6v5_wcss_probe()
1012 desc->firmware_name, sizeof(*wcss)); in q6v5_wcss_probe()
1014 dev_err(&pdev->dev, "failed to allocate rproc\n"); in q6v5_wcss_probe()
1015 return -ENOMEM; in q6v5_wcss_probe()
1018 wcss = rproc->priv; in q6v5_wcss_probe()
1019 wcss->dev = &pdev->dev; in q6v5_wcss_probe()
1020 wcss->version = desc->version; in q6v5_wcss_probe()
1022 wcss->version = desc->version; in q6v5_wcss_probe()
1023 wcss->requires_force_stop = desc->requires_force_stop; in q6v5_wcss_probe()
1033 if (wcss->version == WCSS_QCS404) { in q6v5_wcss_probe()
1047 ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL); in q6v5_wcss_probe()
1051 qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss"); in q6v5_wcss_probe()
1052 qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); in q6v5_wcss_probe()
1054 if (desc->ssctl_id) in q6v5_wcss_probe()
1055 wcss->sysmon = qcom_add_sysmon_subdev(rproc, in q6v5_wcss_probe()
1056 desc->sysmon_name, in q6v5_wcss_probe()
1057 desc->ssctl_id); in q6v5_wcss_probe()
1076 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_remove()
1078 qcom_q6v5_deinit(&wcss->q6v5); in q6v5_wcss_remove()
1108 { .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
1109 { .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
1118 .name = "qcom-q6v5-wcss-pil",