Lines Matching +full:0 +full:x596e8000

31 #define REMOTE_IS_READY				BIT(0)
42 #define IMX8M_DAP_DEBUG 0x28800000
44 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020)
48 #define IMX8M_AudioDSP_REG0 0x100
49 #define IMX8M_AudioDSP_REG1 0x104
50 #define IMX8M_AudioDSP_REG2 0x108
51 #define IMX8M_AudioDSP_REG3 0x10c
57 #define IMX8ULP_SIM_LPAV_REG_SYSCTRL0 0x8
66 #define IMX8ULP_SIP_HIFI_XRDC 0xc200000e
82 RP_MBOX_SUSPEND_SYSTEM = 0xFF11,
83 RP_MBOX_SUSPEND_ACK = 0xFF12,
84 RP_MBOX_RESUME_SYSTEM = 0xFF13,
85 RP_MBOX_RESUME_ACK = 0xFF14,
138 { 0x596e8000, 0x556e8000, 0x00008000, ATT_OWN },
139 { 0x596f0000, 0x556f0000, 0x00008000, ATT_OWN },
140 { 0x596f8000, 0x556f8000, 0x00000800, ATT_OWN | ATT_IRAM},
141 { 0x55700000, 0x55700000, 0x00070000, ATT_OWN },
143 { 0x80000000, 0x80000000, 0x60000000, 0},
148 { 0x596e8000, 0x596e8000, 0x00008000, ATT_OWN },
149 { 0x596f0000, 0x596f0000, 0x00008000, ATT_OWN },
150 { 0x596f8000, 0x596f8000, 0x00000800, ATT_OWN | ATT_IRAM},
151 { 0x59700000, 0x59700000, 0x00070000, ATT_OWN },
153 { 0x80000000, 0x80000000, 0x60000000, 0},
158 { 0x3b6e8000, 0x3b6e8000, 0x00008000, ATT_OWN },
159 { 0x3b6f0000, 0x3b6f0000, 0x00008000, ATT_OWN },
160 { 0x3b6f8000, 0x3b6f8000, 0x00000800, ATT_OWN | ATT_IRAM},
161 { 0x3b700000, 0x3b700000, 0x00040000, ATT_OWN },
163 { 0x40000000, 0x40000000, 0x80000000, 0},
168 { 0x21170000, 0x21170000, 0x00010000, ATT_OWN | ATT_IRAM},
169 { 0x21180000, 0x21180000, 0x00010000, ATT_OWN },
171 { 0x0c000000, 0x80000000, 0x10000000, 0},
172 { 0x30000000, 0x90000000, 0x10000000, 0},
199 return 0; in imx8mp_dsp_reset()
215 arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res); in imx8ulp_dsp_reset()
219 IMX8ULP_SYSCTRL0_DSP_RST, 0); in imx8ulp_dsp_reset()
221 IMX8ULP_SYSCTRL0_DSP_DBG_RST, 0); in imx8ulp_dsp_reset()
223 return 0; in imx8ulp_dsp_reset()
230 .src_start = 0,
246 .src_start = 0,
286 return 0; in imx_dsp_rproc_ready()
288 for (i = 0; i < REMOTE_READY_WAIT_MAX_RETRIES; i++) { in imx_dsp_rproc_ready()
290 return 0; in imx_dsp_rproc_ready()
348 int ret = 0; in imx_dsp_rproc_stop()
355 return 0; in imx_dsp_rproc_stop()
399 for (i = 0; i < dcfg->att_size; i++) { in imx_dsp_rproc_sys_to_da()
406 return 0; in imx_dsp_rproc_sys_to_da()
422 * but there is no need to check for these return values. The index 0
436 rproc_vq_interrupt(priv->rproc, 0); in imx_dsp_rproc_vq_work()
456 dev_dbg(dev, "mbox msg: 0x%x\n", message); in imx_dsp_rproc_rx_tx_callback()
501 return 0; in imx_dsp_rproc_mbox_init()
544 return 0; in imx_dsp_rproc_mbox_init()
586 for (a = 0; a < dcfg->att_size; a++) { in imx_dsp_rproc_add_carveout()
613 of_phandle_iterator_init(&it, np, "memory-region", NULL, 0); in imx_dsp_rproc_add_carveout()
614 while (of_phandle_iterator_next(&it) == 0) { in imx_dsp_rproc_add_carveout()
649 return 0; in imx_dsp_rproc_add_carveout()
674 memset(carveout->va, 0, carveout->len); in imx_dsp_rproc_prepare()
677 return 0; in imx_dsp_rproc_prepare()
685 return 0; in imx_dsp_rproc_unprepare()
708 if (err < 0) in imx_dsp_rproc_kick()
717 return 0; in imx_dsp_rproc_parse_fw()
750 return 0; in imx_dsp_attach_pm_domains()
764 for (i = 0; i < priv->num_domains; i++) { in imx_dsp_attach_pm_domains()
786 return 0; in imx_dsp_attach_pm_domains()
789 while (--i >= 0) { in imx_dsp_attach_pm_domains()
802 return 0; in imx_dsp_detach_pm_domains()
804 for (i = 0; i < priv->num_domains; i++) { in imx_dsp_detach_pm_domains()
809 return 0; in imx_dsp_detach_pm_domains()
829 int ret = 0; in imx_dsp_rproc_detect_mode()
865 for (i = 0; i < DSP_RPROC_CLK_MAX; i++) in imx_dsp_rproc_clk_get()
884 ret = rproc_of_parse_firmware(dev, 0, &fw_name); in imx_dsp_rproc_probe()
933 return 0; in imx_dsp_rproc_probe()
953 return 0; in imx_dsp_rproc_remove()
986 return 0; in imx_dsp_runtime_resume()
998 return 0; in imx_dsp_runtime_suspend()
1019 rproc->ops->kick(rproc, 0); in imx_dsp_load_firmware()
1039 if (ret < 0) { in imx_dsp_suspend()
1063 int ret = 0; in imx_dsp_resume()
1070 return 0; in imx_dsp_resume()
1080 if (ret < 0) { in imx_dsp_resume()
1085 return 0; in imx_dsp_resume()