Lines Matching +full:0 +full:x7f
16 #define MT6358_BUCK_MODE_AUTO 0
54 .enable_mask = BIT(0), \
58 .qi = BIT(0), \
106 .enable_mask = BIT(0), \
111 .qi = BIT(0), \
150 .enable_mask = BIT(0), \
154 .qi = BIT(0), \
202 .enable_mask = BIT(0), \
207 .qi = BIT(0), \
230 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
234 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
238 REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
242 REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
293 0, 12,
301 0, 1, 2, 4, 5, 9, 11, 13,
321 0, 7, 9, 10, 11, 12,
367 if (ret != 0) { in mt6358_get_voltage_sel()
377 for (idx = 0; idx < info->desc.n_voltages; idx++) { in mt6358_get_voltage_sel()
391 if (ret != 0) { in mt6358_get_buck_voltage_sel()
410 if (ret != 0) { in mt6358_get_status()
450 if (ret != 0) { in mt6358_regulator_get_mode()
503 buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
506 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
509 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f,
512 buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f,
515 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
518 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
521 buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f,
524 buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f,
527 buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
530 buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f,
533 MT6358_LDO_VRF12_CON0, 0, 1200000),
535 MT6358_LDO_VIO18_CON0, 0, 1800000),
537 MT6358_LDO_VCAMIO_CON0, 0, 1800000),
538 MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
539 MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
540 MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
541 MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
543 MT6358_LDO_VAUX18_CON0, 0, 1800000),
545 MT6358_LDO_VBIF28_CON0, 0, 2800000),
546 MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
547 MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
548 MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
550 MT6358_LDO_VAUD28_CON0, 0, 2800000),
552 MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf),
554 MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
556 MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
558 MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
560 MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00),
562 MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
564 MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
566 MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00),
568 MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
571 0, MT6358_VCN33_ANA_CON0, 0x300),
574 0, MT6358_VCN33_ANA_CON0, 0x300),
576 MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00),
578 MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
580 MT6358_LDO_VLDO28_CON0_0, 0,
581 MT6358_VLDO28_ANA_CON0, 0x300),
583 MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
585 buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00,
586 MT6358_LDO_VSRAM_CON0, 0x7f),
588 buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00,
589 MT6358_LDO_VSRAM_CON2, 0x7f),
592 MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f,
593 MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f),
595 buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00,
596 MT6358_LDO_VSRAM_CON3, 0x7f),
598 buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00,
599 MT6358_LDO_VSRAM_CON1, 0x7f),
605 buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
608 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
611 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f,
614 buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f,
617 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
620 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
623 buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f,
626 buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f,
629 buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
632 buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f,
635 MT6358_LDO_VRF12_CON0, 0, 1200000),
637 MT6358_LDO_VIO18_CON0, 0, 1800000),
638 MT6366_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
639 MT6366_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
640 MT6366_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
641 MT6366_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
643 MT6358_LDO_VAUX18_CON0, 0, 1800000),
645 MT6358_LDO_VBIF28_CON0, 0, 2800000),
646 MT6366_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
647 MT6366_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
648 MT6366_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
650 MT6358_LDO_VAUD28_CON0, 0, 2800000),
652 MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
654 MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
656 MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
658 MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
660 MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
662 MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
664 MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
667 0, MT6358_VCN33_ANA_CON0, 0x300),
670 0, MT6358_VCN33_ANA_CON0, 0x300),
672 MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
674 MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
676 buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00,
677 MT6358_LDO_VSRAM_CON0, 0x7f),
679 buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00,
680 MT6358_LDO_VSRAM_CON2, 0x7f),
683 MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f,
684 MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f),
686 buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00,
687 MT6358_LDO_VSRAM_CON3, 0x7f),
689 buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00,
690 MT6358_LDO_VSRAM_CON1, 0x7f),
709 for (i = 0; i < max_regulator; i++) { in mt6358_regulator_probe()
724 return 0; in mt6358_regulator_probe()
728 {"mt6358-regulator", 0},