306 	if (ret < 0) {  in ab8500_regulator_enable()
313 		"%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",  in ab8500_regulator_enable()
332 		info->update_mask, 0x0);  in ab8500_regulator_disable()
333 	if (ret < 0) {  in ab8500_regulator_disable()
340 		"%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",  in ab8500_regulator_disable()
342 		info->update_mask, 0x0);  in ab8500_regulator_disable()
360 	if (ret < 0) {  in ab8500_regulator_is_enabled()
362 			"couldn't read 0x%x register\n", info->update_reg);  in ab8500_regulator_is_enabled()
367 		"%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"  in ab8500_regulator_is_enabled()
368 		" 0x%x\n",  in ab8500_regulator_is_enabled()
375 		return 0;  in ab8500_regulator_is_enabled()
402 	int ret = 0;  in ab8500_regulator_set_mode()
462 		if (ret < 0) {  in ab8500_regulator_set_mode()
470 			"0x%x, 0x%x, 0x%x, 0x%x\n",  in ab8500_regulator_set_mode()
549 	if (ret < 0) {  in ab8500_regulator_get_voltage_sel()
557 		"0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",  in ab8500_regulator_get_voltage_sel()
584 	if (ret < 0)  in ab8500_regulator_set_voltage_sel()
589 		"%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"  in ab8500_regulator_set_voltage_sel()
590 		" 0x%x\n",  in ab8500_regulator_set_voltage_sel()
666 		.update_bank		= 0x04,
667 		.update_reg		= 0x09,
668 		.update_mask		= 0x03,
669 		.update_val		= 0x01,
670 		.update_val_idle	= 0x03,
671 		.update_val_normal	= 0x01,
672 		.voltage_bank		= 0x04,
673 		.voltage_reg		= 0x1f,
674 		.voltage_mask		= 0x0f,
689 		.update_bank		= 0x04,
690 		.update_reg		= 0x09,
691 		.update_mask		= 0x0c,
692 		.update_val		= 0x04,
693 		.update_val_idle	= 0x0c,
694 		.update_val_normal	= 0x04,
695 		.voltage_bank		= 0x04,
696 		.voltage_reg		= 0x20,
697 		.voltage_mask		= 0x0f,
712 		.update_bank		= 0x04,
713 		.update_reg		= 0x0a,
714 		.update_mask		= 0x03,
715 		.update_val		= 0x01,
716 		.update_val_idle	= 0x03,
717 		.update_val_normal	= 0x01,
718 		.voltage_bank		= 0x04,
719 		.voltage_reg		= 0x21,
720 		.voltage_mask		= 0x07,
734 		.update_bank		= 0x03,
735 		.update_reg		= 0x80,
736 		.update_mask		= 0x44,
737 		.update_val		= 0x44,
738 		.update_val_idle	= 0x44,
739 		.update_val_normal	= 0x04,
740 		.voltage_bank		= 0x03,
741 		.voltage_reg		= 0x80,
742 		.voltage_mask		= 0x38,
762 		.update_bank		= 0x03,
763 		.update_reg		= 0x80,
764 		.update_mask		= 0x82,
765 		.update_val		= 0x02,
766 		.update_val_idle	= 0x82,
767 		.update_val_normal	= 0x02,
780 		.update_bank		= 0x03,
781 		.update_reg		= 0x83,
782 		.update_mask		= 0x02,
783 		.update_val		= 0x02,
796 		.update_bank		= 0x03,
797 		.update_reg		= 0x83,
798 		.update_mask		= 0x08,
799 		.update_val		= 0x08,
812 		.update_bank		= 0x03,
813 		.update_reg		= 0x83,
814 		.update_mask		= 0x10,
815 		.update_val		= 0x10,
828 		.update_bank		= 0x03,
829 		.update_reg		= 0x83,
830 		.update_mask		= 0x04,
831 		.update_val		= 0x04,
849 		.update_bank		= 0x04,
850 		.update_reg		= 0x06,
851 		.update_mask		= 0x0c,
852 		.update_val		= 0x04,
853 		.update_val_idle	= 0x0c,
854 		.update_val_normal	= 0x04,
878 		.update_bank		= 0x04,
879 		.update_reg		= 0x09,
880 		.update_mask		= 0x03,
881 		.update_val		= 0x01,
882 		.update_val_idle	= 0x03,
883 		.update_val_normal	= 0x01,
884 		.voltage_bank		= 0x04,
885 		.voltage_reg		= 0x1f,
886 		.voltage_mask		= 0x0f,
899 		.update_bank		= 0x04,
900 		.update_reg		= 0x09,
901 		.update_mask		= 0x0c,
902 		.update_val		= 0x04,
903 		.update_val_idle	= 0x0c,
904 		.update_val_normal	= 0x04,
905 		.voltage_bank		= 0x04,
906 		.voltage_reg		= 0x20,
907 		.voltage_mask		= 0x0f,
920 		.update_bank		= 0x04,
921 		.update_reg		= 0x0a,
922 		.update_mask		= 0x03,
923 		.update_val		= 0x01,
924 		.update_val_idle	= 0x03,
925 		.update_val_normal	= 0x01,
926 		.voltage_bank		= 0x04,
927 		.voltage_reg		= 0x21,
928 		.voltage_mask		= 0x07,
942 		.update_bank		= 0x04,
943 		.update_reg		= 0x2e,
944 		.update_mask		= 0x03,
945 		.update_val		= 0x01,
946 		.update_val_idle	= 0x03,
947 		.update_val_normal	= 0x01,
949 		.voltage_bank		= 0x04,
950 		.voltage_reg		= 0x2f,
951 		.voltage_mask		= 0x0f,
965 		.update_bank		= 0x01,
966 		.update_reg		= 0x55,
967 		.update_mask		= 0x18,
968 		.update_val		= 0x10,
969 		.update_val_idle	= 0x18,
970 		.update_val_normal	= 0x10,
971 		.voltage_bank		= 0x01,
972 		.voltage_reg		= 0x55,
973 		.voltage_mask		= 0x07,
987 		.update_bank		= 0x01,
988 		.update_reg		= 0x56,
989 		.update_mask		= 0x18,
990 		.update_val		= 0x10,
991 		.update_val_idle	= 0x18,
992 		.update_val_normal	= 0x10,
993 		.voltage_bank		= 0x01,
994 		.voltage_reg		= 0x56,
995 		.voltage_mask		= 0x07,
1008 		.update_bank		= 0x03,
1009 		.update_reg		= 0x80,
1010 		.update_mask		= 0x44,
1011 		.update_val		= 0x04,
1012 		.update_val_idle	= 0x44,
1013 		.update_val_normal	= 0x04,
1014 		.voltage_bank		= 0x03,
1015 		.voltage_reg		= 0x80,
1016 		.voltage_mask		= 0x38,
1036 		.update_bank		= 0x03,
1037 		.update_reg		= 0x80,
1038 		.update_mask		= 0x82,
1039 		.update_val		= 0x02,
1040 		.update_val_idle	= 0x82,
1041 		.update_val_normal	= 0x02,
1053 		.update_bank		= 0x03,
1054 		.update_reg		= 0x83,
1055 		.update_mask		= 0x02,
1056 		.update_val		= 0x02,
1057 		.voltage_bank		= 0x01,
1058 		.voltage_reg		= 0x57,
1059 		.voltage_mask		= 0x70,
1072 		.update_bank		= 0x03,
1073 		.update_reg		= 0x83,
1074 		.update_mask		= 0x08,
1075 		.update_val		= 0x08,
1076 		.mode_bank		= 0x01,
1077 		.mode_reg		= 0x54,
1078 		.mode_mask		= 0x04,
1079 		.mode_val_idle		= 0x04,
1080 		.mode_val_normal	= 0x00,
1093 		.update_bank		= 0x03,
1094 		.update_reg		= 0x83,
1095 		.update_mask		= 0x10,
1096 		.update_val		= 0x10,
1097 		.mode_bank		= 0x01,
1098 		.mode_reg		= 0x54,
1099 		.mode_mask		= 0x04,
1100 		.mode_val_idle		= 0x04,
1101 		.mode_val_normal	= 0x00,
1113 		.update_bank		= 0x03,
1114 		.update_reg		= 0x83,
1115 		.update_mask		= 0x04,
1116 		.update_val		= 0x04,
1132 		.update_bank		= 0x04,
1133 		.update_reg		= 0x06,
1134 		.update_mask		= 0x0c,
1135 		.update_val		= 0x04,
1136 		.update_val_idle	= 0x0c,
1137 		.update_val_normal	= 0x04,
1138 		.voltage_bank		= 0x04,
1139 		.voltage_reg		= 0x29,
1140 		.voltage_mask		= 0x7,
1168 	 * 0x30, VanaRequestCtrl
1169 	 * 0xc0, VextSupply1RequestCtrl
1171 	REG_INIT(AB8500_REGUREQUESTCTRL2,	0x03, 0x04, 0xf0),
1173 	 * 0x03, VextSupply2RequestCtrl
1174 	 * 0x0c, VextSupply3RequestCtrl
1175 	 * 0x30, Vaux1RequestCtrl
1176 	 * 0xc0, Vaux2RequestCtrl
1178 	REG_INIT(AB8500_REGUREQUESTCTRL3,	0x03, 0x05, 0xff),
1180 	 * 0x03, Vaux3RequestCtrl
1181 	 * 0x04, SwHPReq
1183 	REG_INIT(AB8500_REGUREQUESTCTRL4,	0x03, 0x06, 0x07),
1185 	 * 0x08, VanaSysClkReq1HPValid
1186 	 * 0x20, Vaux1SysClkReq1HPValid
1187 	 * 0x40, Vaux2SysClkReq1HPValid
1188 	 * 0x80, Vaux3SysClkReq1HPValid
1190 	REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1,	0x03, 0x07, 0xe8),
1192 	 * 0x10, VextSupply1SysClkReq1HPValid
1193 	 * 0x20, VextSupply2SysClkReq1HPValid
1194 	 * 0x40, VextSupply3SysClkReq1HPValid
1196 	REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2,	0x03, 0x08, 0x70),
1198 	 * 0x08, VanaHwHPReq1Valid
1199 	 * 0x20, Vaux1HwHPReq1Valid
1200 	 * 0x40, Vaux2HwHPReq1Valid
1201 	 * 0x80, Vaux3HwHPReq1Valid
1203 	REG_INIT(AB8500_REGUHWHPREQ1VALID1,	0x03, 0x09, 0xe8),
1205 	 * 0x01, VextSupply1HwHPReq1Valid
1206 	 * 0x02, VextSupply2HwHPReq1Valid
1207 	 * 0x04, VextSupply3HwHPReq1Valid
1209 	REG_INIT(AB8500_REGUHWHPREQ1VALID2,	0x03, 0x0a, 0x07),
1211 	 * 0x08, VanaHwHPReq2Valid
1212 	 * 0x20, Vaux1HwHPReq2Valid
1213 	 * 0x40, Vaux2HwHPReq2Valid
1214 	 * 0x80, Vaux3HwHPReq2Valid
1216 	REG_INIT(AB8500_REGUHWHPREQ2VALID1,	0x03, 0x0b, 0xe8),
1218 	 * 0x01, VextSupply1HwHPReq2Valid
1219 	 * 0x02, VextSupply2HwHPReq2Valid
1220 	 * 0x04, VextSupply3HwHPReq2Valid
1222 	REG_INIT(AB8500_REGUHWHPREQ2VALID2,	0x03, 0x0c, 0x07),
1224 	 * 0x20, VanaSwHPReqValid
1225 	 * 0x80, Vaux1SwHPReqValid
1227 	REG_INIT(AB8500_REGUSWHPREQVALID1,	0x03, 0x0d, 0xa0),
1229 	 * 0x01, Vaux2SwHPReqValid
1230 	 * 0x02, Vaux3SwHPReqValid
1231 	 * 0x04, VextSupply1SwHPReqValid
1232 	 * 0x08, VextSupply2SwHPReqValid
1233 	 * 0x10, VextSupply3SwHPReqValid
1235 	REG_INIT(AB8500_REGUSWHPREQVALID2,	0x03, 0x0e, 0x1f),
1237 	 * 0x02, SysClkReq2Valid1
1238 	 * 0x04, SysClkReq3Valid1
1239 	 * 0x08, SysClkReq4Valid1
1240 	 * 0x10, SysClkReq5Valid1
1241 	 * 0x20, SysClkReq6Valid1
1242 	 * 0x40, SysClkReq7Valid1
1243 	 * 0x80, SysClkReq8Valid1
1245 	REG_INIT(AB8500_REGUSYSCLKREQVALID1,	0x03, 0x0f, 0xfe),
1247 	 * 0x02, SysClkReq2Valid2
1248 	 * 0x04, SysClkReq3Valid2
1249 	 * 0x08, SysClkReq4Valid2
1250 	 * 0x10, SysClkReq5Valid2
1251 	 * 0x20, SysClkReq6Valid2
1252 	 * 0x40, SysClkReq7Valid2
1253 	 * 0x80, SysClkReq8Valid2
1255 	REG_INIT(AB8500_REGUSYSCLKREQVALID2,	0x03, 0x10, 0xfe),
1257 	 * 0x02, VTVoutEna
1258 	 * 0x04, Vintcore12Ena
1259 	 * 0x38, Vintcore12Sel
1260 	 * 0x40, Vintcore12LP
1261 	 * 0x80, VTVoutLP
1263 	REG_INIT(AB8500_REGUMISC1,		0x03, 0x80, 0xfe),
1265 	 * 0x02, VaudioEna
1266 	 * 0x04, VdmicEna
1267 	 * 0x08, Vamic1Ena
1268 	 * 0x10, Vamic2Ena
1270 	REG_INIT(AB8500_VAUDIOSUPPLY,		0x03, 0x83, 0x1e),
1272 	 * 0x01, Vamic1_dzout
1273 	 * 0x02, Vamic2_dzout
1275 	REG_INIT(AB8500_REGUCTRL1VAMIC,		0x03, 0x84, 0x03),
1277 	 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1278 	 * 0x0c, VanaRegu
1280 	REG_INIT(AB8500_VPLLVANAREGU,		0x04, 0x06, 0x0f),
1282 	 * 0x01, VrefDDREna
1283 	 * 0x02, VrefDDRSleepMode
1285 	REG_INIT(AB8500_VREFDDR,		0x04, 0x07, 0x03),
1287 	 * 0x03, VextSupply1Regu
1288 	 * 0x0c, VextSupply2Regu
1289 	 * 0x30, VextSupply3Regu
1290 	 * 0x40, ExtSupply2Bypass
1291 	 * 0x80, ExtSupply3Bypass
1293 	REG_INIT(AB8500_EXTSUPPLYREGU,		0x04, 0x08, 0xff),
1295 	 * 0x03, Vaux1Regu
1296 	 * 0x0c, Vaux2Regu
1298 	REG_INIT(AB8500_VAUX12REGU,		0x04, 0x09, 0x0f),
1300 	 * 0x03, Vaux3Regu
1302 	REG_INIT(AB8500_VRF1VAUX3REGU,		0x04, 0x0a, 0x03),
1304 	 * 0x0f, Vaux1Sel
1306 	REG_INIT(AB8500_VAUX1SEL,		0x04, 0x1f, 0x0f),
1308 	 * 0x0f, Vaux2Sel
1310 	REG_INIT(AB8500_VAUX2SEL,		0x04, 0x20, 0x0f),
1312 	 * 0x07, Vaux3Sel
1314 	REG_INIT(AB8500_VRF1VAUX3SEL,		0x04, 0x21, 0x07),
1316 	 * 0x01, VextSupply12LP
1318 	REG_INIT(AB8500_REGUCTRL2SPARE,		0x04, 0x22, 0x01),
1320 	 * 0x04, Vaux1Disch
1321 	 * 0x08, Vaux2Disch
1322 	 * 0x10, Vaux3Disch
1323 	 * 0x20, Vintcore12Disch
1324 	 * 0x40, VTVoutDisch
1325 	 * 0x80, VaudioDisch
1327 	REG_INIT(AB8500_REGUCTRLDISCH,		0x04, 0x43, 0xfc),
1329 	 * 0x02, VanaDisch
1330 	 * 0x04, VdmicPullDownEna
1331 	 * 0x10, VdmicDisch
1333 	REG_INIT(AB8500_REGUCTRLDISCH2,		0x04, 0x44, 0x16),
1339 	 * 0x03, VarmRequestCtrl
1340 	 * 0x0c, VsmpsCRequestCtrl
1341 	 * 0x30, VsmpsARequestCtrl
1342 	 * 0xc0, VsmpsBRequestCtrl
1344 	REG_INIT(AB8505_REGUREQUESTCTRL1,	0x03, 0x03, 0xff),
1346 	 * 0x03, VsafeRequestCtrl
1347 	 * 0x0c, VpllRequestCtrl
1348 	 * 0x30, VanaRequestCtrl
1350 	REG_INIT(AB8505_REGUREQUESTCTRL2,	0x03, 0x04, 0x3f),
1352 	 * 0x30, Vaux1RequestCtrl
1353 	 * 0xc0, Vaux2RequestCtrl
1355 	REG_INIT(AB8505_REGUREQUESTCTRL3,	0x03, 0x05, 0xf0),
1357 	 * 0x03, Vaux3RequestCtrl
1358 	 * 0x04, SwHPReq
1360 	REG_INIT(AB8505_REGUREQUESTCTRL4,	0x03, 0x06, 0x07),
1362 	 * 0x01, VsmpsASysClkReq1HPValid
1363 	 * 0x02, VsmpsBSysClkReq1HPValid
1364 	 * 0x04, VsafeSysClkReq1HPValid
1365 	 * 0x08, VanaSysClkReq1HPValid
1366 	 * 0x10, VpllSysClkReq1HPValid
1367 	 * 0x20, Vaux1SysClkReq1HPValid
1368 	 * 0x40, Vaux2SysClkReq1HPValid
1369 	 * 0x80, Vaux3SysClkReq1HPValid
1371 	REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1,	0x03, 0x07, 0xff),
1373 	 * 0x01, VsmpsCSysClkReq1HPValid
1374 	 * 0x02, VarmSysClkReq1HPValid
1375 	 * 0x04, VbbSysClkReq1HPValid
1376 	 * 0x08, VsmpsMSysClkReq1HPValid
1378 	REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2,	0x03, 0x08, 0x0f),
1380 	 * 0x01, VsmpsAHwHPReq1Valid
1381 	 * 0x02, VsmpsBHwHPReq1Valid
1382 	 * 0x04, VsafeHwHPReq1Valid
1383 	 * 0x08, VanaHwHPReq1Valid
1384 	 * 0x10, VpllHwHPReq1Valid
1385 	 * 0x20, Vaux1HwHPReq1Valid
1386 	 * 0x40, Vaux2HwHPReq1Valid
1387 	 * 0x80, Vaux3HwHPReq1Valid
1389 	REG_INIT(AB8505_REGUHWHPREQ1VALID1,	0x03, 0x09, 0xff),
1391 	 * 0x08, VsmpsMHwHPReq1Valid
1393 	REG_INIT(AB8505_REGUHWHPREQ1VALID2,	0x03, 0x0a, 0x08),
1395 	 * 0x01, VsmpsAHwHPReq2Valid
1396 	 * 0x02, VsmpsBHwHPReq2Valid
1397 	 * 0x04, VsafeHwHPReq2Valid
1398 	 * 0x08, VanaHwHPReq2Valid
1399 	 * 0x10, VpllHwHPReq2Valid
1400 	 * 0x20, Vaux1HwHPReq2Valid
1401 	 * 0x40, Vaux2HwHPReq2Valid
1402 	 * 0x80, Vaux3HwHPReq2Valid
1404 	REG_INIT(AB8505_REGUHWHPREQ2VALID1,	0x03, 0x0b, 0xff),
1406 	 * 0x08, VsmpsMHwHPReq2Valid
1408 	REG_INIT(AB8505_REGUHWHPREQ2VALID2,	0x03, 0x0c, 0x08),
1410 	 * 0x01, VsmpsCSwHPReqValid
1411 	 * 0x02, VarmSwHPReqValid
1412 	 * 0x04, VsmpsASwHPReqValid
1413 	 * 0x08, VsmpsBSwHPReqValid
1414 	 * 0x10, VsafeSwHPReqValid
1415 	 * 0x20, VanaSwHPReqValid
1416 	 * 0x40, VpllSwHPReqValid
1417 	 * 0x80, Vaux1SwHPReqValid
1419 	REG_INIT(AB8505_REGUSWHPREQVALID1,	0x03, 0x0d, 0xff),
1421 	 * 0x01, Vaux2SwHPReqValid
1422 	 * 0x02, Vaux3SwHPReqValid
1423 	 * 0x20, VsmpsMSwHPReqValid
1425 	REG_INIT(AB8505_REGUSWHPREQVALID2,	0x03, 0x0e, 0x23),
1427 	 * 0x02, SysClkReq2Valid1
1428 	 * 0x04, SysClkReq3Valid1
1429 	 * 0x08, SysClkReq4Valid1
1431 	REG_INIT(AB8505_REGUSYSCLKREQVALID1,	0x03, 0x0f, 0x0e),
1433 	 * 0x02, SysClkReq2Valid2
1434 	 * 0x04, SysClkReq3Valid2
1435 	 * 0x08, SysClkReq4Valid2
1437 	REG_INIT(AB8505_REGUSYSCLKREQVALID2,	0x03, 0x10, 0x0e),
1439 	 * 0x01, Vaux4SwHPReqValid
1440 	 * 0x02, Vaux4HwHPReq2Valid
1441 	 * 0x04, Vaux4HwHPReq1Valid
1442 	 * 0x08, Vaux4SysClkReq1HPValid
1444 	REG_INIT(AB8505_REGUVAUX4REQVALID,	0x03, 0x11, 0x0f),
1446 	 * 0x02, VadcEna
1447 	 * 0x04, VintCore12Ena
1448 	 * 0x38, VintCore12Sel
1449 	 * 0x40, VintCore12LP
1450 	 * 0x80, VadcLP
1452 	REG_INIT(AB8505_REGUMISC1,		0x03, 0x80, 0xfe),
1454 	 * 0x02, VaudioEna
1455 	 * 0x04, VdmicEna
1456 	 * 0x08, Vamic1Ena
1457 	 * 0x10, Vamic2Ena
1459 	REG_INIT(AB8505_VAUDIOSUPPLY,		0x03, 0x83, 0x1e),
1461 	 * 0x01, Vamic1_dzout
1462 	 * 0x02, Vamic2_dzout
1464 	REG_INIT(AB8505_REGUCTRL1VAMIC,		0x03, 0x84, 0x03),
1466 	 * 0x03, VsmpsARegu
1467 	 * 0x0c, VsmpsASelCtrl
1468 	 * 0x10, VsmpsAAutoMode
1469 	 * 0x20, VsmpsAPWMMode
1471 	REG_INIT(AB8505_VSMPSAREGU,		0x04, 0x03, 0x3f),
1473 	 * 0x03, VsmpsBRegu
1474 	 * 0x0c, VsmpsBSelCtrl
1475 	 * 0x10, VsmpsBAutoMode
1476 	 * 0x20, VsmpsBPWMMode
1478 	REG_INIT(AB8505_VSMPSBREGU,		0x04, 0x04, 0x3f),
1480 	 * 0x03, VsafeRegu
1481 	 * 0x0c, VsafeSelCtrl
1482 	 * 0x10, VsafeAutoMode
1483 	 * 0x20, VsafePWMMode
1485 	REG_INIT(AB8505_VSAFEREGU,		0x04, 0x05, 0x3f),
1487 	 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1488 	 * 0x0c, VanaRegu
1490 	REG_INIT(AB8505_VPLLVANAREGU,		0x04, 0x06, 0x0f),
1492 	 * 0x03, VextSupply1Regu
1493 	 * 0x0c, VextSupply2Regu
1494 	 * 0x30, VextSupply3Regu
1495 	 * 0x40, ExtSupply2Bypass
1496 	 * 0x80, ExtSupply3Bypass
1498 	REG_INIT(AB8505_EXTSUPPLYREGU,		0x04, 0x08, 0xff),
1500 	 * 0x03, Vaux1Regu
1501 	 * 0x0c, Vaux2Regu
1503 	REG_INIT(AB8505_VAUX12REGU,		0x04, 0x09, 0x0f),
1505 	 * 0x0f, Vaux3Regu
1507 	REG_INIT(AB8505_VRF1VAUX3REGU,		0x04, 0x0a, 0x0f),
1509 	 * 0x3f, VsmpsASel1
1511 	REG_INIT(AB8505_VSMPSASEL1,		0x04, 0x13, 0x3f),
1513 	 * 0x3f, VsmpsASel2
1515 	REG_INIT(AB8505_VSMPSASEL2,		0x04, 0x14, 0x3f),
1517 	 * 0x3f, VsmpsASel3
1519 	REG_INIT(AB8505_VSMPSASEL3,		0x04, 0x15, 0x3f),
1521 	 * 0x3f, VsmpsBSel1
1523 	REG_INIT(AB8505_VSMPSBSEL1,		0x04, 0x17, 0x3f),
1525 	 * 0x3f, VsmpsBSel2
1527 	REG_INIT(AB8505_VSMPSBSEL2,		0x04, 0x18, 0x3f),
1529 	 * 0x3f, VsmpsBSel3
1531 	REG_INIT(AB8505_VSMPSBSEL3,		0x04, 0x19, 0x3f),
1533 	 * 0x7f, VsafeSel1
1535 	REG_INIT(AB8505_VSAFESEL1,		0x04, 0x1b, 0x7f),
1537 	 * 0x3f, VsafeSel2
1539 	REG_INIT(AB8505_VSAFESEL2,		0x04, 0x1c, 0x7f),
1541 	 * 0x3f, VsafeSel3
1543 	REG_INIT(AB8505_VSAFESEL3,		0x04, 0x1d, 0x7f),
1545 	 * 0x0f, Vaux1Sel
1547 	REG_INIT(AB8505_VAUX1SEL,		0x04, 0x1f, 0x0f),
1549 	 * 0x0f, Vaux2Sel
1551 	REG_INIT(AB8505_VAUX2SEL,		0x04, 0x20, 0x0f),
1553 	 * 0x07, Vaux3Sel
1554 	 * 0x30, VRF1Sel
1556 	REG_INIT(AB8505_VRF1VAUX3SEL,		0x04, 0x21, 0x37),
1558 	 * 0x03, Vaux4RequestCtrl
1560 	REG_INIT(AB8505_VAUX4REQCTRL,		0x04, 0x2d, 0x03),
1562 	 * 0x03, Vaux4Regu
1564 	REG_INIT(AB8505_VAUX4REGU,		0x04, 0x2e, 0x03),
1566 	 * 0x0f, Vaux4Sel
1568 	REG_INIT(AB8505_VAUX4SEL,		0x04, 0x2f, 0x0f),
1570 	 * 0x04, Vaux1Disch
1571 	 * 0x08, Vaux2Disch
1572 	 * 0x10, Vaux3Disch
1573 	 * 0x20, Vintcore12Disch
1574 	 * 0x40, VTVoutDisch
1575 	 * 0x80, VaudioDisch
1577 	REG_INIT(AB8505_REGUCTRLDISCH,		0x04, 0x43, 0xfc),
1579 	 * 0x02, VanaDisch
1580 	 * 0x04, VdmicPullDownEna
1581 	 * 0x10, VdmicDisch
1583 	REG_INIT(AB8505_REGUCTRLDISCH2,		0x04, 0x44, 0x16),
1585 	 * 0x01, Vaux4Disch
1587 	REG_INIT(AB8505_REGUCTRLDISCH3,		0x04, 0x48, 0x01),
1589 	 * 0x07, Vaux5Sel
1590 	 * 0x08, Vaux5LP
1591 	 * 0x10, Vaux5Ena
1592 	 * 0x20, Vaux5Disch
1593 	 * 0x40, Vaux5DisSfst
1594 	 * 0x80, Vaux5DisPulld
1596 	REG_INIT(AB8505_CTRLVAUX5,		0x01, 0x55, 0xff),
1598 	 * 0x07, Vaux6Sel
1599 	 * 0x08, Vaux6LP
1600 	 * 0x10, Vaux6Ena
1601 	 * 0x80, Vaux6DisPulld
1603 	REG_INIT(AB8505_CTRLVAUX6,		0x01, 0x56, 0x9f),
1681 	/* fix for hardware before ab8500v2.0 */  in ab8500_regulator_register()
1687 			info->voltage_mask = 0xf;  in ab8500_regulator_register()
1699 	return 0;  in ab8500_regulator_register()
1719 	if (err < 0) {  in ab8500_regulator_probe()
1726 	for (i = 0; i < abx500_regulator.info_size; i++) {  in ab8500_regulator_probe()
1733 	return 0;  in ab8500_regulator_probe()
1748 	if (ret != 0)  in ab8500_regulator_init()