1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * drivers/pwm/pwm-tegra.c
5  * Tegra pulse-width-modulation controller driver
7  * Copyright (c) 2010-2020, NVIDIA Corporation.
8  * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11  * 1. 13-bit: Frequency division (SCALE)
12  * 2. 8-bit : Pulse division (DUTY)
13  * 3. 1-bit : Enable bit
18  * achieved is (max rate of source clock) / 256.
19  * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
24  * To achieve 100% duty cycle, program Bit [24] of this register to
28  * -	When PWM is disabled, the output is driven to inactive.
29  * -	It does not allow the current PWM period to complete and
32  * -	If the register is reconfigured while PWM is running,
35  * -	If the user input duty is beyond acceptible limits,
36  *	-EINVAL is returned.
90 	return readl(pc->regs + (offset << 4));  in pwm_readl()
95 	writel(value, pc->regs + (offset << 4));  in pwm_writel()
103 	unsigned long rate, required_clk_rate;  in tegra_pwm_config()  local
118 	 *  min period = max clock limit >> PWM_DUTY_WIDTH  in tegra_pwm_config()
120 	if (period_ns < pc->min_period_ns)  in tegra_pwm_config()
121 		return -EINVAL;  in tegra_pwm_config()
125 	 * cycles at the PWM clock rate will take period_ns nanoseconds.  in tegra_pwm_config()
133 	 * nums_channels == 1 then only the clock rate can be modified  in tegra_pwm_config()
136 	if (pc->soc->num_channels == 1) {  in tegra_pwm_config()
138 		 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches  in tegra_pwm_config()
139 		 * with the maximum possible rate that the controller can  in tegra_pwm_config()
143 		 * required_clk_rate is a reference rate for source clock and  in tegra_pwm_config()
145 		 * source clock rate as required_clk_rate, PWM controller will  in tegra_pwm_config()
151 		err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);  in tegra_pwm_config()
153 			return -EINVAL;  in tegra_pwm_config()
155 		/* Store the new rate for further references */  in tegra_pwm_config()
156 		pc->clk_rate = clk_get_rate(pc->clk);  in tegra_pwm_config()
159 	/* Consider precision in PWM_SCALE_WIDTH rate calculation */  in tegra_pwm_config()
160 	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,  in tegra_pwm_config()
168 	if (rate > 0)  in tegra_pwm_config()
169 		rate--;  in tegra_pwm_config()
171 		return -EINVAL;  in tegra_pwm_config()
174 	 * Make sure that the rate will fit in the register's frequency  in tegra_pwm_config()
177 	if (rate >> PWM_SCALE_WIDTH)  in tegra_pwm_config()
178 		return -EINVAL;  in tegra_pwm_config()
180 	val |= rate << PWM_SCALE_SHIFT;  in tegra_pwm_config()
187 		err = pm_runtime_resume_and_get(pc->dev);  in tegra_pwm_config()
193 	pwm_writel(pc, pwm->hwpwm, val);  in tegra_pwm_config()
199 		pm_runtime_put(pc->dev);  in tegra_pwm_config()
210 	rc = pm_runtime_resume_and_get(pc->dev);  in tegra_pwm_enable()
214 	val = pwm_readl(pc, pwm->hwpwm);  in tegra_pwm_enable()
216 	pwm_writel(pc, pwm->hwpwm, val);  in tegra_pwm_enable()
226 	val = pwm_readl(pc, pwm->hwpwm);  in tegra_pwm_disable()
228 	pwm_writel(pc, pwm->hwpwm, val);  in tegra_pwm_disable()
230 	pm_runtime_put_sync(pc->dev);  in tegra_pwm_disable()
237 	bool enabled = pwm->state.enabled;  in tegra_pwm_apply()
239 	if (state->polarity != PWM_POLARITY_NORMAL)  in tegra_pwm_apply()
240 		return -EINVAL;  in tegra_pwm_apply()
242 	if (!state->enabled) {  in tegra_pwm_apply()
249 	err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);  in tegra_pwm_apply()
269 	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);  in tegra_pwm_probe()
271 		return -ENOMEM;  in tegra_pwm_probe()
273 	pc->soc = of_device_get_match_data(&pdev->dev);  in tegra_pwm_probe()
274 	pc->dev = &pdev->dev;  in tegra_pwm_probe()
276 	pc->regs = devm_platform_ioremap_resource(pdev, 0);  in tegra_pwm_probe()
277 	if (IS_ERR(pc->regs))  in tegra_pwm_probe()
278 		return PTR_ERR(pc->regs);  in tegra_pwm_probe()
282 	pc->clk = devm_clk_get(&pdev->dev, NULL);  in tegra_pwm_probe()
283 	if (IS_ERR(pc->clk))  in tegra_pwm_probe()
284 		return PTR_ERR(pc->clk);  in tegra_pwm_probe()
286 	ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);  in tegra_pwm_probe()
290 	pm_runtime_enable(&pdev->dev);  in tegra_pwm_probe()
291 	ret = pm_runtime_resume_and_get(&pdev->dev);  in tegra_pwm_probe()
296 	ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency);  in tegra_pwm_probe()
298 		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);  in tegra_pwm_probe()
307 	pc->clk_rate = clk_get_rate(pc->clk);  in tegra_pwm_probe()
310 	pc->min_period_ns =  in tegra_pwm_probe()
311 	    (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;  in tegra_pwm_probe()
313 	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");  in tegra_pwm_probe()
314 	if (IS_ERR(pc->rst)) {  in tegra_pwm_probe()
315 		ret = PTR_ERR(pc->rst);  in tegra_pwm_probe()
316 		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);  in tegra_pwm_probe()
320 	reset_control_deassert(pc->rst);  in tegra_pwm_probe()
322 	pc->chip.dev = &pdev->dev;  in tegra_pwm_probe()
323 	pc->chip.ops = &tegra_pwm_ops;  in tegra_pwm_probe()
324 	pc->chip.npwm = pc->soc->num_channels;  in tegra_pwm_probe()
326 	ret = pwmchip_add(&pc->chip);  in tegra_pwm_probe()
328 		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);  in tegra_pwm_probe()
329 		reset_control_assert(pc->rst);  in tegra_pwm_probe()
333 	pm_runtime_put(&pdev->dev);  in tegra_pwm_probe()
337 	pm_runtime_put_sync_suspend(&pdev->dev);  in tegra_pwm_probe()
338 	pm_runtime_force_suspend(&pdev->dev);  in tegra_pwm_probe()
346 	pwmchip_remove(&pc->chip);  in tegra_pwm_remove()
348 	reset_control_assert(pc->rst);  in tegra_pwm_remove()
350 	pm_runtime_force_suspend(&pdev->dev);  in tegra_pwm_remove()
360 	clk_disable_unprepare(pc->clk);  in tegra_pwm_runtime_suspend()
364 		clk_prepare_enable(pc->clk);  in tegra_pwm_runtime_suspend()
380 	err = clk_prepare_enable(pc->clk);  in tegra_pwm_runtime_resume()
405 	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
406 	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
407 	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
421 		.name = "tegra-pwm",
434 MODULE_ALIAS("platform:tegra-pwm");