Lines Matching +full:sun50i +full:- +full:h6 +full:- +full:pwm
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
22 #include <linux/pwm.h>
48 #define PWM_PRD(prd) (((prd) - 1) << 16)
102 return readl(chip->base + offset); in sun4i_pwm_readl()
108 writel(val, chip->base + offset); in sun4i_pwm_writel()
112 struct pwm_device *pwm, in sun4i_pwm_get_state() argument
120 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
125 * PWM chapter in H6 manual has a diagram which explains that if bypass in sun4i_pwm_get_state()
129 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
130 sun4i_pwm->data->has_direct_mod_clk_output) { in sun4i_pwm_get_state()
131 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); in sun4i_pwm_get_state()
132 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); in sun4i_pwm_get_state()
133 state->polarity = PWM_POLARITY_NORMAL; in sun4i_pwm_get_state()
134 state->enabled = true; in sun4i_pwm_get_state()
138 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
139 sun4i_pwm->data->has_prescaler_bypass) in sun4i_pwm_get_state()
142 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
147 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
148 state->polarity = PWM_POLARITY_NORMAL; in sun4i_pwm_get_state()
150 state->polarity = PWM_POLARITY_INVERSED; in sun4i_pwm_get_state()
152 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
153 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
154 state->enabled = true; in sun4i_pwm_get_state()
156 state->enabled = false; in sun4i_pwm_get_state()
158 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
161 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
164 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
175 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_calculate()
177 *bypass = sun4i_pwm->data->has_direct_mod_clk_output && in sun4i_pwm_calculate()
178 state->enabled && in sun4i_pwm_calculate()
179 (state->period * clk_rate >= NSEC_PER_SEC) && in sun4i_pwm_calculate()
180 (state->period * clk_rate < 2 * NSEC_PER_SEC) && in sun4i_pwm_calculate()
181 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); in sun4i_pwm_calculate()
187 if (sun4i_pwm->data->has_prescaler_bypass) { in sun4i_pwm_calculate()
195 div = clk_rate * state->period + NSEC_PER_SEC / 2; in sun4i_pwm_calculate()
197 if (div - 1 > PWM_PRD_MASK) in sun4i_pwm_calculate()
211 div = div * state->period; in sun4i_pwm_calculate()
213 if (div - 1 <= PWM_PRD_MASK) in sun4i_pwm_calculate()
217 if (div - 1 > PWM_PRD_MASK) in sun4i_pwm_calculate()
218 return -EINVAL; in sun4i_pwm_calculate()
222 div *= state->duty_cycle; in sun4i_pwm_calculate()
223 do_div(div, state->period); in sun4i_pwm_calculate()
230 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in sun4i_pwm_apply() argument
240 pwm_get_state(pwm, &cstate); in sun4i_pwm_apply()
243 ret = clk_prepare_enable(sun4i_pwm->clk); in sun4i_pwm_apply()
245 dev_err(chip->dev, "failed to enable PWM clock\n"); in sun4i_pwm_apply()
253 dev_err(chip->dev, "period exceeds the maximum value\n"); in sun4i_pwm_apply()
255 clk_disable_unprepare(sun4i_pwm->clk); in sun4i_pwm_apply()
259 spin_lock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
262 if (sun4i_pwm->data->has_direct_mod_clk_output) { in sun4i_pwm_apply()
264 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
267 spin_unlock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
271 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
274 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { in sun4i_pwm_apply()
276 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
279 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); in sun4i_pwm_apply()
280 ctrl |= BIT_CH(prescaler, pwm->hwpwm); in sun4i_pwm_apply()
284 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_apply()
286 if (state->polarity != PWM_POLARITY_NORMAL) in sun4i_pwm_apply()
287 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); in sun4i_pwm_apply()
289 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); in sun4i_pwm_apply()
291 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
293 if (state->enabled) in sun4i_pwm_apply()
294 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); in sun4i_pwm_apply()
298 spin_unlock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
300 if (state->enabled) in sun4i_pwm_apply()
310 spin_lock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
312 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
313 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); in sun4i_pwm_apply()
315 spin_unlock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
317 clk_disable_unprepare(sun4i_pwm->clk); in sun4i_pwm_apply()
357 .compatible = "allwinner,sun4i-a10-pwm",
360 .compatible = "allwinner,sun5i-a10s-pwm",
363 .compatible = "allwinner,sun5i-a13-pwm",
366 .compatible = "allwinner,sun7i-a20-pwm",
369 .compatible = "allwinner,sun8i-h3-pwm",
372 .compatible = "allwinner,sun50i-a64-pwm",
375 .compatible = "allwinner,sun50i-h6-pwm",
388 sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL); in sun4i_pwm_probe()
390 return -ENOMEM; in sun4i_pwm_probe()
392 sun4ichip->data = of_device_get_match_data(&pdev->dev); in sun4i_pwm_probe()
393 if (!sun4ichip->data) in sun4i_pwm_probe()
394 return -ENODEV; in sun4i_pwm_probe()
396 sun4ichip->base = devm_platform_ioremap_resource(pdev, 0); in sun4i_pwm_probe()
397 if (IS_ERR(sun4ichip->base)) in sun4i_pwm_probe()
398 return PTR_ERR(sun4ichip->base); in sun4i_pwm_probe()
404 * Some variants (e.g. H6) need another clock to access the in sun4i_pwm_probe()
408 * unnamed one of the PWM device) and if this is not found we fall in sun4i_pwm_probe()
409 * back to the first clock of the PWM. in sun4i_pwm_probe()
411 sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod"); in sun4i_pwm_probe()
412 if (IS_ERR(sun4ichip->clk)) in sun4i_pwm_probe()
413 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), in sun4i_pwm_probe()
416 if (!sun4ichip->clk) { in sun4i_pwm_probe()
417 sun4ichip->clk = devm_clk_get(&pdev->dev, NULL); in sun4i_pwm_probe()
418 if (IS_ERR(sun4ichip->clk)) in sun4i_pwm_probe()
419 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), in sun4i_pwm_probe()
423 sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); in sun4i_pwm_probe()
424 if (IS_ERR(sun4ichip->bus_clk)) in sun4i_pwm_probe()
425 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk), in sun4i_pwm_probe()
428 sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in sun4i_pwm_probe()
429 if (IS_ERR(sun4ichip->rst)) in sun4i_pwm_probe()
430 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst), in sun4i_pwm_probe()
434 ret = reset_control_deassert(sun4ichip->rst); in sun4i_pwm_probe()
436 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n", in sun4i_pwm_probe()
445 ret = clk_prepare_enable(sun4ichip->bus_clk); in sun4i_pwm_probe()
447 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n", in sun4i_pwm_probe()
452 sun4ichip->chip.dev = &pdev->dev; in sun4i_pwm_probe()
453 sun4ichip->chip.ops = &sun4i_pwm_ops; in sun4i_pwm_probe()
454 sun4ichip->chip.npwm = sun4ichip->data->npwm; in sun4i_pwm_probe()
456 spin_lock_init(&sun4ichip->ctrl_lock); in sun4i_pwm_probe()
458 ret = pwmchip_add(&sun4ichip->chip); in sun4i_pwm_probe()
460 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); in sun4i_pwm_probe()
469 clk_disable_unprepare(sun4ichip->bus_clk); in sun4i_pwm_probe()
471 reset_control_assert(sun4ichip->rst); in sun4i_pwm_probe()
480 pwmchip_remove(&sun4ichip->chip); in sun4i_pwm_remove()
482 clk_disable_unprepare(sun4ichip->bus_clk); in sun4i_pwm_remove()
483 reset_control_assert(sun4ichip->rst); in sun4i_pwm_remove()
490 .name = "sun4i-pwm",
498 MODULE_ALIAS("platform:sun4i-pwm");
499 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
500 MODULE_DESCRIPTION("Allwinner sun4i PWM driver");