Lines Matching +full:capture +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
12 #include <linux/mfd/stm32-timers.h>
38 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ member
50 regmap_read(dev->regmap, TIM_CCER, &ccer); in active_channels()
59 return regmap_write(dev->regmap, TIM_CCR1, value); in write_ccrx()
61 return regmap_write(dev->regmap, TIM_CCR2, value); in write_ccrx()
63 return regmap_write(dev->regmap, TIM_CCR3, value); in write_ccrx()
65 return regmap_write(dev->regmap, TIM_CCR4, value); in write_ccrx()
67 return -EINVAL; in write_ccrx()
76 * Capture using PWM input mode:
98 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
100 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
101 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
105 * - Period = t2 - t0
106 * - Duty cycle = t1 - t0
112 struct device *parent = priv->chip.dev->parent; in stm32_pwm_raw_capture()
117 /* Ensure registers have been updated, enable counter and capture */ in stm32_pwm_raw_capture()
118 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); in stm32_pwm_raw_capture()
119 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); in stm32_pwm_raw_capture()
121 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ in stm32_pwm_raw_capture()
122 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; in stm32_pwm_raw_capture()
123 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; in stm32_pwm_raw_capture()
124 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; in stm32_pwm_raw_capture()
125 regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen); in stm32_pwm_raw_capture()
129 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. in stm32_pwm_raw_capture()
130 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } in stm32_pwm_raw_capture()
133 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, in stm32_pwm_raw_capture()
138 /* Period: t2 - t0 (take care of counter overflow) */ in stm32_pwm_raw_capture()
139 if (priv->capture[0] <= priv->capture[2]) in stm32_pwm_raw_capture()
140 *raw_prd = priv->capture[2] - priv->capture[0]; in stm32_pwm_raw_capture()
142 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; in stm32_pwm_raw_capture()
144 /* Duty cycle capture requires at least two capture units */ in stm32_pwm_raw_capture()
145 if (pwm->chip->npwm < 2) in stm32_pwm_raw_capture()
147 else if (priv->capture[0] <= priv->capture[3]) in stm32_pwm_raw_capture()
148 *raw_dty = priv->capture[3] - priv->capture[0]; in stm32_pwm_raw_capture()
150 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; in stm32_pwm_raw_capture()
155 * falling edge triggers new capture on TI2/4 before DMA in stm32_pwm_raw_capture()
156 * had a chance to read CCR2/4. It means capture[1] in stm32_pwm_raw_capture()
159 *raw_dty -= *raw_prd; in stm32_pwm_raw_capture()
163 regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0); in stm32_pwm_raw_capture()
164 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); in stm32_pwm_raw_capture()
179 mutex_lock(&priv->lock); in stm32_pwm_capture()
182 ret = -EBUSY; in stm32_pwm_capture()
186 ret = clk_enable(priv->clk); in stm32_pwm_capture()
188 dev_err(priv->chip.dev, "failed to enable counter clock\n"); in stm32_pwm_capture()
192 rate = clk_get_rate(priv->clk); in stm32_pwm_capture()
194 ret = -EINVAL; in stm32_pwm_capture()
202 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { in stm32_pwm_capture()
207 regmap_write(priv->regmap, TIM_ARR, priv->max_arr); in stm32_pwm_capture()
208 regmap_write(priv->regmap, TIM_PSC, psc); in stm32_pwm_capture()
211 regmap_update_bits(priv->regmap, in stm32_pwm_capture()
212 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
213 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? in stm32_pwm_capture()
217 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ in stm32_pwm_capture()
218 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? in stm32_pwm_capture()
219 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? in stm32_pwm_capture()
227 * Got a capture. Try to improve accuracy at high rates: in stm32_pwm_capture()
228 * - decrease counter clock prescaler, scale up to max rate. in stm32_pwm_capture()
229 * - use input prescaler, capture once every /2 /4 or /8 edges. in stm32_pwm_capture()
232 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ in stm32_pwm_capture()
236 scale = priv->max_arr; /* bellow resolution, use max scale */ in stm32_pwm_capture()
242 regmap_write(priv->regmap, TIM_PSC, psc); in stm32_pwm_capture()
255 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) in stm32_pwm_capture()
265 regmap_update_bits(priv->regmap, in stm32_pwm_capture()
266 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
278 * capture starts on high side (before falling edge). in stm32_pwm_capture()
279 * Example with icpsc to capture on each 4 events: in stm32_pwm_capture()
281 * start 1st capture 2nd capture in stm32_pwm_capture()
292 * Capture0: .<----------------------------->. in stm32_pwm_capture()
293 * Capture1: .<-------------------------->. . in stm32_pwm_capture()
295 * Period: .<------> . . in stm32_pwm_capture()
299 * - Period = Capture0 / icpsc in stm32_pwm_capture()
300 * - Duty = Period - Low side = Period - (Capture0 - Capture1) in stm32_pwm_capture()
302 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); in stm32_pwm_capture()
307 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); in stm32_pwm_capture()
309 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); in stm32_pwm_capture()
311 regmap_write(priv->regmap, TIM_CCER, 0); in stm32_pwm_capture()
312 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); in stm32_pwm_capture()
313 regmap_write(priv->regmap, TIM_PSC, 0); in stm32_pwm_capture()
315 clk_disable(priv->clk); in stm32_pwm_capture()
317 mutex_unlock(&priv->lock); in stm32_pwm_capture()
330 div = (unsigned long long)clk_get_rate(priv->clk) * period_ns; in stm32_pwm_config()
335 while (div > priv->max_arr) { in stm32_pwm_config()
344 return -EINVAL; in stm32_pwm_config()
347 * All channels share the same prescaler and counter so when two in stm32_pwm_config()
348 * channels are active at the same time we can't change them in stm32_pwm_config()
353 regmap_read(priv->regmap, TIM_PSC, &psc); in stm32_pwm_config()
354 regmap_read(priv->regmap, TIM_ARR, &arr); in stm32_pwm_config()
356 if ((psc != prescaler) || (arr != prd - 1)) in stm32_pwm_config()
357 return -EBUSY; in stm32_pwm_config()
360 regmap_write(priv->regmap, TIM_PSC, prescaler); in stm32_pwm_config()
361 regmap_write(priv->regmap, TIM_ARR, prd - 1); in stm32_pwm_config()
362 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); in stm32_pwm_config()
376 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); in stm32_pwm_config()
378 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); in stm32_pwm_config()
380 regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE); in stm32_pwm_config()
391 if (priv->have_complementary_output) in stm32_pwm_set_polarity()
394 regmap_update_bits(priv->regmap, TIM_CCER, mask, in stm32_pwm_set_polarity()
405 ret = clk_enable(priv->clk); in stm32_pwm_enable()
411 if (priv->have_complementary_output) in stm32_pwm_enable()
414 regmap_update_bits(priv->regmap, TIM_CCER, mask, mask); in stm32_pwm_enable()
417 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); in stm32_pwm_enable()
420 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); in stm32_pwm_enable()
431 if (priv->have_complementary_output) in stm32_pwm_disable()
434 regmap_update_bits(priv->regmap, TIM_CCER, mask, 0); in stm32_pwm_disable()
436 /* When all channels are disabled, we can disable the controller */ in stm32_pwm_disable()
438 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); in stm32_pwm_disable()
440 clk_disable(priv->clk); in stm32_pwm_disable()
450 enabled = pwm->state.enabled; in stm32_pwm_apply()
452 if (enabled && !state->enabled) { in stm32_pwm_apply()
453 stm32_pwm_disable(priv, pwm->hwpwm); in stm32_pwm_apply()
457 if (state->polarity != pwm->state.polarity) in stm32_pwm_apply()
458 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity); in stm32_pwm_apply()
460 ret = stm32_pwm_config(priv, pwm->hwpwm, in stm32_pwm_apply()
461 state->duty_cycle, state->period); in stm32_pwm_apply()
465 if (!enabled && state->enabled) in stm32_pwm_apply()
466 ret = stm32_pwm_enable(priv, pwm->hwpwm); in stm32_pwm_apply()
477 /* protect common prescaler for all active channels */ in stm32_pwm_apply_locked()
478 mutex_lock(&priv->lock); in stm32_pwm_apply_locked()
480 mutex_unlock(&priv->lock); in stm32_pwm_apply_locked()
488 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
494 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index); in stm32_pwm_set_breakinput()
495 u32 bke = TIM_BDTR_BKE(bi->index); in stm32_pwm_set_breakinput()
496 u32 bkp = TIM_BDTR_BKP(bi->index); in stm32_pwm_set_breakinput()
497 u32 bkf = TIM_BDTR_BKF(bi->index); in stm32_pwm_set_breakinput()
501 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke; in stm32_pwm_set_breakinput()
503 if (bi->level) in stm32_pwm_set_breakinput()
506 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); in stm32_pwm_set_breakinput()
508 regmap_read(priv->regmap, TIM_BDTR, &bdtr); in stm32_pwm_set_breakinput()
510 return (bdtr & bke) ? 0 : -EINVAL; in stm32_pwm_set_breakinput()
518 for (i = 0; i < priv->num_breakinputs; i++) { in stm32_pwm_apply_breakinputs()
519 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]); in stm32_pwm_apply_breakinputs()
544 return -EINVAL; in stm32_pwm_probe_breakinputs()
546 priv->num_breakinputs = nb; in stm32_pwm_probe_breakinputs()
549 (u32 *)priv->breakinputs, array_size); in stm32_pwm_probe_breakinputs()
553 for (i = 0; i < priv->num_breakinputs; i++) { in stm32_pwm_probe_breakinputs()
554 if (priv->breakinputs[i].index > 1 || in stm32_pwm_probe_breakinputs()
555 priv->breakinputs[i].level > 1 || in stm32_pwm_probe_breakinputs()
556 priv->breakinputs[i].filter > 15) in stm32_pwm_probe_breakinputs()
557 return -EINVAL; in stm32_pwm_probe_breakinputs()
571 regmap_update_bits(priv->regmap, in stm32_pwm_detect_complementary()
573 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_pwm_detect_complementary()
574 regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0); in stm32_pwm_detect_complementary()
576 priv->have_complementary_output = (ccer != 0); in stm32_pwm_detect_complementary()
585 * If channels enable bits don't exist writing 1 will have no in stm32_pwm_detect_channels()
588 regmap_update_bits(priv->regmap, in stm32_pwm_detect_channels()
590 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_pwm_detect_channels()
591 regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0); in stm32_pwm_detect_channels()
610 struct device *dev = &pdev->dev; in stm32_pwm_probe()
611 struct device_node *np = dev->of_node; in stm32_pwm_probe()
612 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); in stm32_pwm_probe()
618 return -ENOMEM; in stm32_pwm_probe()
620 mutex_init(&priv->lock); in stm32_pwm_probe()
621 priv->regmap = ddata->regmap; in stm32_pwm_probe()
622 priv->clk = ddata->clk; in stm32_pwm_probe()
623 priv->max_arr = ddata->max_arr; in stm32_pwm_probe()
625 if (!priv->regmap || !priv->clk) in stm32_pwm_probe()
626 return -EINVAL; in stm32_pwm_probe()
634 priv->chip.dev = dev; in stm32_pwm_probe()
635 priv->chip.ops = &stm32pwm_ops; in stm32_pwm_probe()
636 priv->chip.npwm = stm32_pwm_detect_channels(priv); in stm32_pwm_probe()
638 ret = pwmchip_add(&priv->chip); in stm32_pwm_probe()
652 for (i = 0; i < priv->chip.npwm; i++) in stm32_pwm_remove()
653 pwm_disable(&priv->chip.pwms[i]); in stm32_pwm_remove()
655 pwmchip_remove(&priv->chip); in stm32_pwm_remove()
666 /* Look for active channels */ in stm32_pwm_suspend()
669 for (i = 0; i < priv->chip.npwm; i++) { in stm32_pwm_suspend()
673 i, priv->chip.pwms[i].label); in stm32_pwm_suspend()
674 return -EBUSY; in stm32_pwm_suspend()
697 { .compatible = "st,stm32-pwm", },
706 .name = "stm32-pwm",
713 MODULE_ALIAS("platform:stm32-pwm");