1 // SPDX-License-Identifier: GPL-2.0-only
8  * enough to be briefly explained. It consists of one 8-bit counter. The PWM
14  * Let cnt[7:0] be the counter, clocked at 32kHz:
15  * +-----------+--------+--------------+-----------+---------------+
17  * +-----------+--------+--------------+-----------+---------------+
22  * +-----------+--------+--------------+-----------+---------------+
25  * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26  * - The hardware cannot atomically set the prescaler and the counter value,
28  * - The counter is not reset if you switch the prescaler which leads
30  * - The duty cycle will switch immediately and not after a complete cycle.
31  * - Depending on the actual implementation, disabling the PWM might have
54 #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)	(1 << (7 - (prescaler)))
63  *   max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
64  *   max_duty_cycle = 1 << (7 - prescaler)
69  * NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing
78 	regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
80 	regmap_write((priv)->regmap, (priv)->offset + (reg), (val))
100 	state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;  in sl28cpld_pwm_get_state()
103 	state->period = SL28CPLD_PWM_PERIOD(prescaler);  in sl28cpld_pwm_get_state()
106 	state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);  in sl28cpld_pwm_get_state()
107 	state->polarity = PWM_POLARITY_NORMAL;  in sl28cpld_pwm_get_state()
117 	state->duty_cycle = min(state->duty_cycle, state->period);  in sl28cpld_pwm_get_state()
130 	if (state->polarity != PWM_POLARITY_NORMAL)  in sl28cpld_pwm_apply()
131 		return -EINVAL;  in sl28cpld_pwm_apply()
137 	prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);  in sl28cpld_pwm_apply()
141 		return -ERANGE;  in sl28cpld_pwm_apply()
144 	if (state->enabled)  in sl28cpld_pwm_apply()
147 	cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);  in sl28cpld_pwm_apply()
153 	 * care about the frequency because its "all-one" in either case.  in sl28cpld_pwm_apply()
173 	write_duty_cycle_first = pwm->state.period > state->period;  in sl28cpld_pwm_apply()
206 	if (!pdev->dev.parent) {  in sl28cpld_pwm_probe()
207 		dev_err(&pdev->dev, "no parent device\n");  in sl28cpld_pwm_probe()
208 		return -ENODEV;  in sl28cpld_pwm_probe()
211 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in sl28cpld_pwm_probe()
213 		return -ENOMEM;  in sl28cpld_pwm_probe()
215 	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);  in sl28cpld_pwm_probe()
216 	if (!priv->regmap) {  in sl28cpld_pwm_probe()
217 		dev_err(&pdev->dev, "could not get parent regmap\n");  in sl28cpld_pwm_probe()
218 		return -ENODEV;  in sl28cpld_pwm_probe()
221 	ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);  in sl28cpld_pwm_probe()
223 		dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",  in sl28cpld_pwm_probe()
225 		return -EINVAL;  in sl28cpld_pwm_probe()
229 	chip = &priv->pwm_chip;  in sl28cpld_pwm_probe()
230 	chip->dev = &pdev->dev;  in sl28cpld_pwm_probe()
231 	chip->ops = &sl28cpld_pwm_ops;  in sl28cpld_pwm_probe()
232 	chip->npwm = 1;  in sl28cpld_pwm_probe()
234 	ret = devm_pwmchip_add(&pdev->dev, &priv->pwm_chip);  in sl28cpld_pwm_probe()
236 		dev_err(&pdev->dev, "failed to add PWM chip (%pe)",  in sl28cpld_pwm_probe()
245 	{ .compatible = "kontron,sl28cpld-pwm" },
253 		.name = "sl28cpld-pwm",