1 // SPDX-License-Identifier: GPL-2.0-only
65 	u32 enable_conf = pc->data->enable_conf;  in rockchip_pwm_get_state()
71 	ret = clk_enable(pc->pclk);  in rockchip_pwm_get_state()
75 	ret = clk_enable(pc->clk);  in rockchip_pwm_get_state()
79 	clk_rate = clk_get_rate(pc->clk);  in rockchip_pwm_get_state()
81 	tmp = readl_relaxed(pc->base + pc->data->regs.period);  in rockchip_pwm_get_state()
82 	tmp *= pc->data->prescaler * NSEC_PER_SEC;  in rockchip_pwm_get_state()
83 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);  in rockchip_pwm_get_state()
85 	tmp = readl_relaxed(pc->base + pc->data->regs.duty);  in rockchip_pwm_get_state()
86 	tmp *= pc->data->prescaler * NSEC_PER_SEC;  in rockchip_pwm_get_state()
87 	state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);  in rockchip_pwm_get_state()
89 	val = readl_relaxed(pc->base + pc->data->regs.ctrl);  in rockchip_pwm_get_state()
90 	state->enabled = (val & enable_conf) == enable_conf;  in rockchip_pwm_get_state()
92 	if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))  in rockchip_pwm_get_state()
93 		state->polarity = PWM_POLARITY_INVERSED;  in rockchip_pwm_get_state()
95 		state->polarity = PWM_POLARITY_NORMAL;  in rockchip_pwm_get_state()
97 	clk_disable(pc->clk);  in rockchip_pwm_get_state()
98 	clk_disable(pc->pclk);  in rockchip_pwm_get_state()
109 	clk_rate = clk_get_rate(pc->clk);  in rockchip_pwm_config()
116 	div = clk_rate * state->period;  in rockchip_pwm_config()
118 				       pc->data->prescaler * NSEC_PER_SEC);  in rockchip_pwm_config()
120 	div = clk_rate * state->duty_cycle;  in rockchip_pwm_config()
121 	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);  in rockchip_pwm_config()
127 	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);  in rockchip_pwm_config()
128 	if (pc->data->supports_lock) {  in rockchip_pwm_config()
130 		writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);  in rockchip_pwm_config()
133 	writel(period, pc->base + pc->data->regs.period);  in rockchip_pwm_config()
134 	writel(duty, pc->base + pc->data->regs.duty);  in rockchip_pwm_config()
136 	if (pc->data->supports_polarity) {  in rockchip_pwm_config()
138 		if (state->polarity == PWM_POLARITY_INVERSED)  in rockchip_pwm_config()
149 	if (pc->data->supports_lock)  in rockchip_pwm_config()
152 	writel(ctrl, pc->base + pc->data->regs.ctrl);  in rockchip_pwm_config()
160 	u32 enable_conf = pc->data->enable_conf;  in rockchip_pwm_enable()
165 		ret = clk_enable(pc->clk);  in rockchip_pwm_enable()
170 	val = readl_relaxed(pc->base + pc->data->regs.ctrl);  in rockchip_pwm_enable()
177 	writel_relaxed(val, pc->base + pc->data->regs.ctrl);  in rockchip_pwm_enable()
180 		clk_disable(pc->clk);  in rockchip_pwm_enable()
193 	ret = clk_enable(pc->pclk);  in rockchip_pwm_apply()
197 	ret = clk_enable(pc->clk);  in rockchip_pwm_apply()
204 	if (state->polarity != curstate.polarity && enabled &&  in rockchip_pwm_apply()
205 	    !pc->data->supports_lock) {  in rockchip_pwm_apply()
213 	if (state->enabled != enabled) {  in rockchip_pwm_apply()
214 		ret = rockchip_pwm_enable(chip, pwm, state->enabled);  in rockchip_pwm_apply()
220 	clk_disable(pc->clk);  in rockchip_pwm_apply()
221 	clk_disable(pc->pclk);  in rockchip_pwm_apply()
288 	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
289 	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
290 	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
291 	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
304 	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);  in rockchip_pwm_probe()
306 		return -EINVAL;  in rockchip_pwm_probe()
308 	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);  in rockchip_pwm_probe()
310 		return -ENOMEM;  in rockchip_pwm_probe()
312 	pc->base = devm_platform_ioremap_resource(pdev, 0);  in rockchip_pwm_probe()
313 	if (IS_ERR(pc->base))  in rockchip_pwm_probe()
314 		return PTR_ERR(pc->base);  in rockchip_pwm_probe()
316 	pc->clk = devm_clk_get(&pdev->dev, "pwm");  in rockchip_pwm_probe()
317 	if (IS_ERR(pc->clk)) {  in rockchip_pwm_probe()
318 		pc->clk = devm_clk_get(&pdev->dev, NULL);  in rockchip_pwm_probe()
319 		if (IS_ERR(pc->clk))  in rockchip_pwm_probe()
320 			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),  in rockchip_pwm_probe()
324 	count = of_count_phandle_with_args(pdev->dev.of_node,  in rockchip_pwm_probe()
325 					   "clocks", "#clock-cells");  in rockchip_pwm_probe()
327 		pc->pclk = devm_clk_get(&pdev->dev, "pclk");  in rockchip_pwm_probe()
329 		pc->pclk = pc->clk;  in rockchip_pwm_probe()
331 	if (IS_ERR(pc->pclk))  in rockchip_pwm_probe()
332 		return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n");  in rockchip_pwm_probe()
334 	ret = clk_prepare_enable(pc->clk);  in rockchip_pwm_probe()
336 		return dev_err_probe(&pdev->dev, ret, "Can't prepare enable PWM clk\n");  in rockchip_pwm_probe()
338 	ret = clk_prepare_enable(pc->pclk);  in rockchip_pwm_probe()
340 		dev_err_probe(&pdev->dev, ret, "Can't prepare enable APB clk\n");  in rockchip_pwm_probe()
346 	pc->data = id->data;  in rockchip_pwm_probe()
347 	pc->chip.dev = &pdev->dev;  in rockchip_pwm_probe()
348 	pc->chip.ops = &rockchip_pwm_ops;  in rockchip_pwm_probe()
349 	pc->chip.npwm = 1;  in rockchip_pwm_probe()
351 	enable_conf = pc->data->enable_conf;  in rockchip_pwm_probe()
352 	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);  in rockchip_pwm_probe()
355 	ret = pwmchip_add(&pc->chip);  in rockchip_pwm_probe()
357 		dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");  in rockchip_pwm_probe()
363 		clk_disable(pc->clk);  in rockchip_pwm_probe()
365 	clk_disable(pc->pclk);  in rockchip_pwm_probe()
370 	clk_disable_unprepare(pc->pclk);  in rockchip_pwm_probe()
372 	clk_disable_unprepare(pc->clk);  in rockchip_pwm_probe()
381 	pwmchip_remove(&pc->chip);  in rockchip_pwm_remove()
383 	clk_unprepare(pc->pclk);  in rockchip_pwm_remove()
384 	clk_unprepare(pc->clk);  in rockchip_pwm_remove()
391 		.name = "rockchip-pwm",