92 static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)  in tpu_pwm_write()  argument
94 	void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET  in tpu_pwm_write()
95 			   + tpd->channel * TPU_CHANNEL_SIZE;  in tpu_pwm_write()
100 static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,  in tpu_pwm_set_pin()  argument
105 	dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",  in tpu_pwm_set_pin()
106 		tpd->channel, states[state]);  in tpu_pwm_set_pin()
110 		tpu_pwm_write(tpd, TPU_TIORn,  in tpu_pwm_set_pin()
111 			      tpd->polarity == PWM_POLARITY_INVERSED ?  in tpu_pwm_set_pin()
115 		tpu_pwm_write(tpd, TPU_TIORn,  in tpu_pwm_set_pin()
116 			      tpd->polarity == PWM_POLARITY_INVERSED ?  in tpu_pwm_set_pin()
120 		tpu_pwm_write(tpd, TPU_TIORn,  in tpu_pwm_set_pin()
121 			      tpd->polarity == PWM_POLARITY_INVERSED ?  in tpu_pwm_set_pin()
127 static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)  in tpu_pwm_start_stop()  argument
132 	spin_lock_irqsave(&tpd->tpu->lock, flags);  in tpu_pwm_start_stop()
133 	value = ioread16(tpd->tpu->base + TPU_TSTR);  in tpu_pwm_start_stop()
136 		value |= 1 << tpd->channel;  in tpu_pwm_start_stop()
138 		value &= ~(1 << tpd->channel);  in tpu_pwm_start_stop()
140 	iowrite16(value, tpd->tpu->base + TPU_TSTR);  in tpu_pwm_start_stop()
141 	spin_unlock_irqrestore(&tpd->tpu->lock, flags);  in tpu_pwm_start_stop()
144 static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)  in tpu_pwm_timer_start()  argument
148 	if (!tpd->timer_on) {  in tpu_pwm_timer_start()
150 		pm_runtime_get_sync(&tpd->tpu->pdev->dev);  in tpu_pwm_timer_start()
151 		ret = clk_prepare_enable(tpd->tpu->clk);  in tpu_pwm_timer_start()
153 			dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");  in tpu_pwm_timer_start()
156 		tpd->timer_on = true;  in tpu_pwm_timer_start()
164 	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);  in tpu_pwm_timer_start()
165 	tpu_pwm_start_stop(tpd, false);  in tpu_pwm_timer_start()
175 	tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |  in tpu_pwm_timer_start()
176 		      tpd->prescaler);  in tpu_pwm_timer_start()
177 	tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);  in tpu_pwm_timer_start()
178 	tpu_pwm_set_pin(tpd, TPU_PIN_PWM);  in tpu_pwm_timer_start()
179 	tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);  in tpu_pwm_timer_start()
180 	tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);  in tpu_pwm_timer_start()
182 	dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",  in tpu_pwm_timer_start()
183 		tpd->channel, tpd->duty, tpd->period);  in tpu_pwm_timer_start()
186 	tpu_pwm_start_stop(tpd, true);  in tpu_pwm_timer_start()
191 static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)  in tpu_pwm_timer_stop()  argument
193 	if (!tpd->timer_on)  in tpu_pwm_timer_stop()
197 	tpu_pwm_start_stop(tpd, false);  in tpu_pwm_timer_stop()
200 	clk_disable_unprepare(tpd->tpu->clk);  in tpu_pwm_timer_stop()
201 	pm_runtime_put(&tpd->tpu->pdev->dev);  in tpu_pwm_timer_stop()
203 	tpd->timer_on = false;  in tpu_pwm_timer_stop()
213 	struct tpu_pwm_device *tpd;  in tpu_pwm_request()  local
218 	tpd = kzalloc(sizeof(*tpd), GFP_KERNEL);  in tpu_pwm_request()
219 	if (tpd == NULL)  in tpu_pwm_request()
222 	tpd->tpu = tpu;  in tpu_pwm_request()
223 	tpd->channel = pwm->hwpwm;  in tpu_pwm_request()
224 	tpd->polarity = PWM_POLARITY_NORMAL;  in tpu_pwm_request()
225 	tpd->prescaler = 0;  in tpu_pwm_request()
226 	tpd->period = 0;  in tpu_pwm_request()
227 	tpd->duty = 0;  in tpu_pwm_request()
229 	tpd->timer_on = false;  in tpu_pwm_request()
231 	pwm_set_chip_data(pwm, tpd);  in tpu_pwm_request()
238 	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);  in tpu_pwm_free()  local
240 	tpu_pwm_timer_stop(tpd);  in tpu_pwm_free()
241 	kfree(tpd);  in tpu_pwm_free()
247 	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);  in tpu_pwm_config()  local
314 	if (tpd->prescaler == prescaler && tpd->period == period)  in tpu_pwm_config()
317 	tpd->prescaler = prescaler;  in tpu_pwm_config()
318 	tpd->period = period;  in tpu_pwm_config()
319 	tpd->duty = duty;  in tpu_pwm_config()
325 	if (duty_only && tpd->timer_on) {  in tpu_pwm_config()
331 		tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);  in tpu_pwm_config()
332 		dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,  in tpu_pwm_config()
333 			tpd->duty);  in tpu_pwm_config()
336 		ret = tpu_pwm_timer_start(tpd);  in tpu_pwm_config()
346 		tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);  in tpu_pwm_config()
347 		tpu_pwm_timer_stop(tpd);  in tpu_pwm_config()
356 	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);  in tpu_pwm_set_polarity()  local
358 	tpd->polarity = polarity;  in tpu_pwm_set_polarity()
365 	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);  in tpu_pwm_enable()  local
368 	ret = tpu_pwm_timer_start(tpd);  in tpu_pwm_enable()
376 	if (tpd->duty == 0 || tpd->duty == tpd->period) {  in tpu_pwm_enable()
377 		tpu_pwm_set_pin(tpd, tpd->duty ?  in tpu_pwm_enable()
379 		tpu_pwm_timer_stop(tpd);  in tpu_pwm_enable()
387 	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);  in tpu_pwm_disable()  local
390 	tpu_pwm_timer_start(tpd);  in tpu_pwm_disable()
391 	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);  in tpu_pwm_disable()
392 	tpu_pwm_timer_stop(tpd);  in tpu_pwm_disable()