Lines Matching +full:io +full:- +full:channel +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
13 * Setting the duty cycle will disable and re-enable the PWM output.
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
33 #include <linux/clk-provider.h>
35 #include <linux/io.h>
94 struct clk_mux mux; member
123 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_request() local
124 struct device *dev = chip->dev; in meson_pwm_request()
127 if (channel->clk_parent) { in meson_pwm_request()
128 err = clk_set_parent(channel->clk, channel->clk_parent); in meson_pwm_request()
131 __clk_get_name(channel->clk_parent), in meson_pwm_request()
132 __clk_get_name(channel->clk), err); in meson_pwm_request()
137 err = clk_prepare_enable(channel->clk); in meson_pwm_request()
140 __clk_get_name(channel->clk), err); in meson_pwm_request()
150 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_free() local
152 clk_disable_unprepare(channel->clk); in meson_pwm_free()
158 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_calc() local
162 duty = state->duty_cycle; in meson_pwm_calc()
163 period = state->period; in meson_pwm_calc()
165 if (state->polarity == PWM_POLARITY_INVERSED) in meson_pwm_calc()
166 duty = period - duty; in meson_pwm_calc()
168 fin_freq = clk_get_rate(channel->clk); in meson_pwm_calc()
170 dev_err(meson->chip.dev, "invalid source clock frequency\n"); in meson_pwm_calc()
171 return -EINVAL; in meson_pwm_calc()
174 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); in meson_pwm_calc()
178 dev_err(meson->chip.dev, "unable to get period pre_div\n"); in meson_pwm_calc()
179 return -EINVAL; in meson_pwm_calc()
184 dev_err(meson->chip.dev, "unable to get period cnt\n"); in meson_pwm_calc()
185 return -EINVAL; in meson_pwm_calc()
188 dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period, in meson_pwm_calc()
192 channel->pre_div = pre_div; in meson_pwm_calc()
193 channel->hi = cnt; in meson_pwm_calc()
194 channel->lo = 0; in meson_pwm_calc()
196 channel->pre_div = pre_div; in meson_pwm_calc()
197 channel->hi = 0; in meson_pwm_calc()
198 channel->lo = cnt; in meson_pwm_calc()
204 dev_err(meson->chip.dev, "unable to get duty cycle\n"); in meson_pwm_calc()
205 return -EINVAL; in meson_pwm_calc()
208 dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n", in meson_pwm_calc()
211 channel->pre_div = pre_div; in meson_pwm_calc()
212 channel->hi = duty_cnt; in meson_pwm_calc()
213 channel->lo = cnt - duty_cnt; in meson_pwm_calc()
221 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_enable() local
226 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; in meson_pwm_enable()
228 spin_lock_irqsave(&meson->lock, flags); in meson_pwm_enable()
230 value = readl(meson->base + REG_MISC_AB); in meson_pwm_enable()
231 value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift); in meson_pwm_enable()
232 value |= channel->pre_div << channel_data->clk_div_shift; in meson_pwm_enable()
233 value |= channel_data->clk_en_mask; in meson_pwm_enable()
234 writel(value, meson->base + REG_MISC_AB); in meson_pwm_enable()
236 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) | in meson_pwm_enable()
237 FIELD_PREP(PWM_LOW_MASK, channel->lo); in meson_pwm_enable()
238 writel(value, meson->base + channel_data->reg_offset); in meson_pwm_enable()
240 value = readl(meson->base + REG_MISC_AB); in meson_pwm_enable()
241 value |= channel_data->pwm_en_mask; in meson_pwm_enable()
242 writel(value, meson->base + REG_MISC_AB); in meson_pwm_enable()
244 spin_unlock_irqrestore(&meson->lock, flags); in meson_pwm_enable()
252 spin_lock_irqsave(&meson->lock, flags); in meson_pwm_disable()
254 value = readl(meson->base + REG_MISC_AB); in meson_pwm_disable()
255 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask; in meson_pwm_disable()
256 writel(value, meson->base + REG_MISC_AB); in meson_pwm_disable()
258 spin_unlock_irqrestore(&meson->lock, flags); in meson_pwm_disable()
265 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_apply() local
268 if (!state->enabled) { in meson_pwm_apply()
269 if (state->polarity == PWM_POLARITY_INVERSED) { in meson_pwm_apply()
282 channel->pre_div = 0; in meson_pwm_apply()
283 channel->hi = ~0; in meson_pwm_apply()
284 channel->lo = 0; in meson_pwm_apply()
305 struct meson_pwm_channel *channel; in meson_pwm_cnt_to_ns() local
310 channel = &meson->channels[pwm->hwpwm]; in meson_pwm_cnt_to_ns()
312 fin_freq = clk_get_rate(channel->clk); in meson_pwm_cnt_to_ns()
318 return cnt * fin_ns * (channel->pre_div + 1); in meson_pwm_cnt_to_ns()
326 struct meson_pwm_channel *channel; in meson_pwm_get_state() local
332 channel = &meson->channels[pwm->hwpwm]; in meson_pwm_get_state()
333 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; in meson_pwm_get_state()
335 value = readl(meson->base + REG_MISC_AB); in meson_pwm_get_state()
337 tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask; in meson_pwm_get_state()
338 state->enabled = (value & tmp) == tmp; in meson_pwm_get_state()
340 tmp = value >> channel_data->clk_div_shift; in meson_pwm_get_state()
341 channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp); in meson_pwm_get_state()
343 value = readl(meson->base + channel_data->reg_offset); in meson_pwm_get_state()
345 channel->lo = FIELD_GET(PWM_LOW_MASK, value); in meson_pwm_get_state()
346 channel->hi = FIELD_GET(PWM_HIGH_MASK, value); in meson_pwm_get_state()
348 if (channel->lo == 0) { in meson_pwm_get_state()
349 state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi); in meson_pwm_get_state()
350 state->duty_cycle = state->period; in meson_pwm_get_state()
351 } else if (channel->lo >= channel->hi) { in meson_pwm_get_state()
352 state->period = meson_pwm_cnt_to_ns(chip, pwm, in meson_pwm_get_state()
353 channel->lo + channel->hi); in meson_pwm_get_state()
354 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, in meson_pwm_get_state()
355 channel->hi); in meson_pwm_get_state()
357 state->period = 0; in meson_pwm_get_state()
358 state->duty_cycle = 0; in meson_pwm_get_state()
448 .compatible = "amlogic,meson8b-pwm",
452 .compatible = "amlogic,meson-gxbb-pwm",
456 .compatible = "amlogic,meson-gxbb-ao-pwm",
460 .compatible = "amlogic,meson-axg-ee-pwm",
464 .compatible = "amlogic,meson-axg-ao-pwm",
468 .compatible = "amlogic,meson-g12a-ee-pwm",
472 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
476 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
485 struct device *dev = meson->chip.dev; in meson_pwm_init_channels()
491 for (i = 0; i < meson->chip.npwm; i++) { in meson_pwm_init_channels()
492 struct meson_pwm_channel *channel = &meson->channels[i]; in meson_pwm_init_channels() local
494 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); in meson_pwm_init_channels()
499 init.parent_names = meson->data->parent_names; in meson_pwm_init_channels()
500 init.num_parents = meson->data->num_parents; in meson_pwm_init_channels()
502 channel->mux.reg = meson->base + REG_MISC_AB; in meson_pwm_init_channels()
503 channel->mux.shift = in meson_pwm_init_channels()
505 channel->mux.mask = MISC_CLK_SEL_MASK; in meson_pwm_init_channels()
506 channel->mux.flags = 0; in meson_pwm_init_channels()
507 channel->mux.lock = &meson->lock; in meson_pwm_init_channels()
508 channel->mux.table = NULL; in meson_pwm_init_channels()
509 channel->mux.hw.init = &init; in meson_pwm_init_channels()
511 channel->clk = devm_clk_register(dev, &channel->mux.hw); in meson_pwm_init_channels()
512 if (IS_ERR(channel->clk)) { in meson_pwm_init_channels()
513 err = PTR_ERR(channel->clk); in meson_pwm_init_channels()
520 channel->clk_parent = devm_clk_get_optional(dev, name); in meson_pwm_init_channels()
521 if (IS_ERR(channel->clk_parent)) in meson_pwm_init_channels()
522 return PTR_ERR(channel->clk_parent); in meson_pwm_init_channels()
533 meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL); in meson_pwm_probe()
535 return -ENOMEM; in meson_pwm_probe()
537 meson->base = devm_platform_ioremap_resource(pdev, 0); in meson_pwm_probe()
538 if (IS_ERR(meson->base)) in meson_pwm_probe()
539 return PTR_ERR(meson->base); in meson_pwm_probe()
541 spin_lock_init(&meson->lock); in meson_pwm_probe()
542 meson->chip.dev = &pdev->dev; in meson_pwm_probe()
543 meson->chip.ops = &meson_pwm_ops; in meson_pwm_probe()
544 meson->chip.npwm = MESON_NUM_PWMS; in meson_pwm_probe()
546 meson->data = of_device_get_match_data(&pdev->dev); in meson_pwm_probe()
552 err = devm_pwmchip_add(&pdev->dev, &meson->chip); in meson_pwm_probe()
554 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err); in meson_pwm_probe()
563 .name = "meson-pwm",