1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (c) 2014-2015, Imagination Technologies
7  * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
43  * PWM period is specified with a timebase register,
45  * specified in step periods, in the [0, $timebase] range.
46  * In other words, the timebase imposes the duty cycle
47  * resolution. Therefore, let's constraint the timebase to
49  * Imposing a minimum timebase, will impose a maximum PWM frequency.
83 	writel(val, imgchip->base + reg);  in img_pwm_writel()
88 	return readl(imgchip->base + reg);  in img_pwm_readl()
94 	u32 val, div, duty, timebase;  in img_pwm_config()  local
97 	unsigned int max_timebase = imgchip->data->max_timebase;  in img_pwm_config()
100 	if (period_ns < imgchip->min_period_ns ||  in img_pwm_config()
101 	    period_ns > imgchip->max_period_ns) {  in img_pwm_config()
102 		dev_err(chip->dev, "configured period not in range\n");  in img_pwm_config()
103 		return -ERANGE;  in img_pwm_config()
106 	input_clk_hz = clk_get_rate(imgchip->pwm_clk);  in img_pwm_config()
112 		timebase = DIV_ROUND_UP(mul, 1);  in img_pwm_config()
115 		timebase = DIV_ROUND_UP(mul, 8);  in img_pwm_config()
118 		timebase = DIV_ROUND_UP(mul, 64);  in img_pwm_config()
121 		timebase = DIV_ROUND_UP(mul, 512);  in img_pwm_config()
123 		dev_err(chip->dev,  in img_pwm_config()
124 			"failed to configure timebase steps/divider value\n");  in img_pwm_config()
125 		return -EINVAL;  in img_pwm_config()
128 	duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);  in img_pwm_config()
130 	ret = pm_runtime_resume_and_get(chip->dev);  in img_pwm_config()
135 	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));  in img_pwm_config()
137 		PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);  in img_pwm_config()
141 	      (timebase << PWM_CH_CFG_TMBASE_SHIFT);  in img_pwm_config()
142 	img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);  in img_pwm_config()
144 	pm_runtime_mark_last_busy(chip->dev);  in img_pwm_config()
145 	pm_runtime_put_autosuspend(chip->dev);  in img_pwm_config()
156 	ret = pm_runtime_resume_and_get(chip->dev);  in img_pwm_enable()
161 	val |= BIT(pwm->hwpwm);  in img_pwm_enable()
164 	regmap_update_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,  in img_pwm_enable()
166 			   PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);  in img_pwm_enable()
177 	val &= ~BIT(pwm->hwpwm);  in img_pwm_disable()
180 	pm_runtime_mark_last_busy(chip->dev);  in img_pwm_disable()
181 	pm_runtime_put_autosuspend(chip->dev);  in img_pwm_disable()
189 	if (state->polarity != PWM_POLARITY_NORMAL)  in img_pwm_apply()
190 		return -EINVAL;  in img_pwm_apply()
192 	if (!state->enabled) {  in img_pwm_apply()
193 		if (pwm->state.enabled)  in img_pwm_apply()
199 	err = img_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);  in img_pwm_apply()
203 	if (!pwm->state.enabled)  in img_pwm_apply()
220 		.compatible = "img,pistachio-pwm",
231 	clk_disable_unprepare(imgchip->pwm_clk);  in img_pwm_runtime_suspend()
232 	clk_disable_unprepare(imgchip->sys_clk);  in img_pwm_runtime_suspend()
242 	ret = clk_prepare_enable(imgchip->sys_clk);  in img_pwm_runtime_resume()
248 	ret = clk_prepare_enable(imgchip->pwm_clk);  in img_pwm_runtime_resume()
251 		clk_disable_unprepare(imgchip->sys_clk);  in img_pwm_runtime_resume()
266 	imgchip = devm_kzalloc(&pdev->dev, sizeof(*imgchip), GFP_KERNEL);  in img_pwm_probe()
268 		return -ENOMEM;  in img_pwm_probe()
270 	imgchip->dev = &pdev->dev;  in img_pwm_probe()
272 	imgchip->base = devm_platform_ioremap_resource(pdev, 0);  in img_pwm_probe()
273 	if (IS_ERR(imgchip->base))  in img_pwm_probe()
274 		return PTR_ERR(imgchip->base);  in img_pwm_probe()
276 	of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);  in img_pwm_probe()
278 		return -ENODEV;  in img_pwm_probe()
279 	imgchip->data = of_dev_id->data;  in img_pwm_probe()
281 	imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,  in img_pwm_probe()
282 							       "img,cr-periph");  in img_pwm_probe()
283 	if (IS_ERR(imgchip->periph_regs))  in img_pwm_probe()
284 		return PTR_ERR(imgchip->periph_regs);  in img_pwm_probe()
286 	imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");  in img_pwm_probe()
287 	if (IS_ERR(imgchip->sys_clk)) {  in img_pwm_probe()
288 		dev_err(&pdev->dev, "failed to get system clock\n");  in img_pwm_probe()
289 		return PTR_ERR(imgchip->sys_clk);  in img_pwm_probe()
292 	imgchip->pwm_clk = devm_clk_get(&pdev->dev, "imgchip");  in img_pwm_probe()
293 	if (IS_ERR(imgchip->pwm_clk)) {  in img_pwm_probe()
294 		dev_err(&pdev->dev, "failed to get imgchip clock\n");  in img_pwm_probe()
295 		return PTR_ERR(imgchip->pwm_clk);  in img_pwm_probe()
300 	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);  in img_pwm_probe()
301 	pm_runtime_use_autosuspend(&pdev->dev);  in img_pwm_probe()
302 	pm_runtime_enable(&pdev->dev);  in img_pwm_probe()
303 	if (!pm_runtime_enabled(&pdev->dev)) {  in img_pwm_probe()
304 		ret = img_pwm_runtime_resume(&pdev->dev);  in img_pwm_probe()
309 	clk_rate = clk_get_rate(imgchip->pwm_clk);  in img_pwm_probe()
311 		dev_err(&pdev->dev, "imgchip clock has no frequency\n");  in img_pwm_probe()
312 		ret = -EINVAL;  in img_pwm_probe()
317 	val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;  in img_pwm_probe()
319 	imgchip->max_period_ns = val;  in img_pwm_probe()
323 	imgchip->min_period_ns = val;  in img_pwm_probe()
325 	imgchip->chip.dev = &pdev->dev;  in img_pwm_probe()
326 	imgchip->chip.ops = &img_pwm_ops;  in img_pwm_probe()
327 	imgchip->chip.npwm = IMG_PWM_NPWM;  in img_pwm_probe()
329 	ret = pwmchip_add(&imgchip->chip);  in img_pwm_probe()
331 		dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);  in img_pwm_probe()
338 	if (!pm_runtime_enabled(&pdev->dev))  in img_pwm_probe()
339 		img_pwm_runtime_suspend(&pdev->dev);  in img_pwm_probe()
341 	pm_runtime_disable(&pdev->dev);  in img_pwm_probe()
342 	pm_runtime_dont_use_autosuspend(&pdev->dev);  in img_pwm_probe()
350 	pm_runtime_disable(&pdev->dev);  in img_pwm_remove()
351 	if (!pm_runtime_status_suspended(&pdev->dev))  in img_pwm_remove()
352 		img_pwm_runtime_suspend(&pdev->dev);  in img_pwm_remove()
354 	pwmchip_remove(&imgchip->chip);  in img_pwm_remove()
371 	for (i = 0; i < imgchip->chip.npwm; i++)  in img_pwm_suspend()
372 		imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,  in img_pwm_suspend()
375 	imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);  in img_pwm_suspend()
392 	for (i = 0; i < imgchip->chip.npwm; i++)  in img_pwm_resume()
394 			       imgchip->suspend_ch_cfg[i]);  in img_pwm_resume()
396 	img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);  in img_pwm_resume()
398 	for (i = 0; i < imgchip->chip.npwm; i++)  in img_pwm_resume()
399 		if (imgchip->suspend_ctrl_cfg & BIT(i))  in img_pwm_resume()
400 			regmap_update_bits(imgchip->periph_regs,  in img_pwm_resume()
422 		.name = "img-pwm",