1 // SPDX-License-Identifier: GPL-2.0-or-later
41  * Maximum control word value allowed when variable-frequency PWM is used as a
42  * clock for the constant-frequency PMW.
64 		return __raw_readl(p->base + offset);  in brcmstb_pwm_readl()
66 		return readl_relaxed(p->base + offset);  in brcmstb_pwm_readl()
73 		__raw_writel(value, p->base + offset);  in brcmstb_pwm_writel()
75 		writel_relaxed(value, p->base + offset);  in brcmstb_pwm_writel()
84  * Fv is derived from the variable frequency output. The variable frequency
87  * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
89  * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
101 	unsigned int channel = pwm->hwpwm;  in brcmstb_pwm_config()
111 		pc = PWM_ON_PERIOD_MAX - 1;  in brcmstb_pwm_config()
119 		 * Calculate the base rate from base frequency and current  in brcmstb_pwm_config()
122 		rate = (u64)clk_get_rate(p->clk) * (u64)cword;  in brcmstb_pwm_config()
133 			return -EINVAL;  in brcmstb_pwm_config()
141 		 * frequency generator to output a 50% duty cycle variable  in brcmstb_pwm_config()
142 		 * frequency which is used as input clock to the fixed  in brcmstb_pwm_config()
143 		 * frequency generator.  in brcmstb_pwm_config()
152 			return -EINVAL;  in brcmstb_pwm_config()
157 	 * Configure the defined "cword" value to have the variable frequency  in brcmstb_pwm_config()
158 	 * generator output a base frequency for the constant frequency  in brcmstb_pwm_config()
164 	/* Select constant frequency signal output */  in brcmstb_pwm_config()
177 					  unsigned int channel, bool enable)  in brcmstb_pwm_enable_set()  argument
179 	unsigned int shift = channel * CTRL_CHAN_OFFS;  in brcmstb_pwm_enable_set()  local
184 	if (enable) {  in brcmstb_pwm_enable_set()
185 		value &= ~(CTRL_OEB << shift);  in brcmstb_pwm_enable_set()
186 		value |= (CTRL_START | CTRL_OPENDRAIN) << shift;  in brcmstb_pwm_enable_set()
188 		value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);  in brcmstb_pwm_enable_set()
189 		value |= CTRL_OEB << shift;  in brcmstb_pwm_enable_set()
201 	if (state->polarity != PWM_POLARITY_NORMAL)  in brcmstb_pwm_apply()
202 		return -EINVAL;  in brcmstb_pwm_apply()
204 	if (!state->enabled) {  in brcmstb_pwm_apply()
205 		if (pwm->state.enabled)  in brcmstb_pwm_apply()
206 			brcmstb_pwm_enable_set(p, pwm->hwpwm, false);  in brcmstb_pwm_apply()
211 	err = brcmstb_pwm_config(chip, pwm, state->duty_cycle, state->period);  in brcmstb_pwm_apply()
215 	if (!pwm->state.enabled)  in brcmstb_pwm_apply()
216 		brcmstb_pwm_enable_set(p, pwm->hwpwm, true);  in brcmstb_pwm_apply()
227 	{ .compatible = "brcm,bcm7038-pwm", },
237 	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);  in brcmstb_pwm_probe()
239 		return -ENOMEM;  in brcmstb_pwm_probe()
241 	p->clk = devm_clk_get(&pdev->dev, NULL);  in brcmstb_pwm_probe()
242 	if (IS_ERR(p->clk)) {  in brcmstb_pwm_probe()
243 		dev_err(&pdev->dev, "failed to obtain clock\n");  in brcmstb_pwm_probe()
244 		return PTR_ERR(p->clk);  in brcmstb_pwm_probe()
247 	ret = clk_prepare_enable(p->clk);  in brcmstb_pwm_probe()
249 		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);  in brcmstb_pwm_probe()
255 	p->chip.dev = &pdev->dev;  in brcmstb_pwm_probe()
256 	p->chip.ops = &brcmstb_pwm_ops;  in brcmstb_pwm_probe()
257 	p->chip.npwm = 2;  in brcmstb_pwm_probe()
259 	p->base = devm_platform_ioremap_resource(pdev, 0);  in brcmstb_pwm_probe()
260 	if (IS_ERR(p->base)) {  in brcmstb_pwm_probe()
261 		ret = PTR_ERR(p->base);  in brcmstb_pwm_probe()
265 	ret = pwmchip_add(&p->chip);  in brcmstb_pwm_probe()
267 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);  in brcmstb_pwm_probe()
274 	clk_disable_unprepare(p->clk);  in brcmstb_pwm_probe()
282 	pwmchip_remove(&p->chip);  in brcmstb_pwm_remove()
283 	clk_disable_unprepare(p->clk);  in brcmstb_pwm_remove()
293 	clk_disable(p->clk);  in brcmstb_pwm_suspend()
302 	clk_enable(p->clk);  in brcmstb_pwm_resume()
315 		.name = "pwm-brcmstb",
324 MODULE_ALIAS("platform:pwm-brcmstb");