1 // SPDX-License-Identifier: GPL-2.0-only
8  * Links to reference manuals for the supported PWM chips can be found in
12  * - Periods start with the inactive level.
13  * - Hardware has to be stopped in general to update settings.
16  * - When atmel_pwm_apply() is called with state->enabled=false a change in
17  *   state->polarity isn't honored.
18  * - Instead of sleeping to wait for a completed period, the interrupt
30 #include <linux/pwm.h>
33 /* The following is global registers for PWM controller */
41 /* The following register is PWM channel related registers */
51 /* The following registers for PWM v1 */
56 /* The following registers for PWM v2 */
89 	 * pending we delay disabling the PWM until the new configuration is
90 	 * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
109 	return readl_relaxed(chip->base + offset);  in atmel_pwm_readl()
115 	writel_relaxed(val, chip->base + offset);  in atmel_pwm_writel()
145 	chip->update_pending &= ~isr;  in atmel_pwm_update_pending()
150 	spin_lock(&chip->lock);  in atmel_pwm_set_pending()
158 	chip->update_pending |= (1 << ch);  in atmel_pwm_set_pending()
160 	spin_unlock(&chip->lock);  in atmel_pwm_set_pending()
167 	spin_lock(&chip->lock);  in atmel_pwm_test_pending()
169 	if (chip->update_pending & (1 << ch)) {  in atmel_pwm_test_pending()
172 		if (chip->update_pending & (1 << ch))  in atmel_pwm_test_pending()
176 	spin_unlock(&chip->lock);  in atmel_pwm_test_pending()
190 	return ret ? -ETIMEDOUT : 0;  in atmel_pwm_wait_nonpending()
195 					     const struct pwm_state *state,  in atmel_pwm_calculate_cprd_and_pres()  argument
199 	unsigned long long cycles = state->period;  in atmel_pwm_calculate_cprd_and_pres()
211 	shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;  in atmel_pwm_calculate_cprd_and_pres()
214 		dev_err(chip->dev, "pres exceeds the maximum value\n");  in atmel_pwm_calculate_cprd_and_pres()
215 		return -EINVAL;  in atmel_pwm_calculate_cprd_and_pres()
228 static void atmel_pwm_calculate_cdty(const struct pwm_state *state,  in atmel_pwm_calculate_cdty()  argument
232 	unsigned long long cycles = state->duty_cycle;  in atmel_pwm_calculate_cdty()
237 	*cdty = cprd - cycles;  in atmel_pwm_calculate_cdty()
240 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,  in atmel_pwm_update_cdty()  argument
246 	if (atmel_pwm->data->regs.duty_upd ==  in atmel_pwm_update_cdty()
247 	    atmel_pwm->data->regs.period_upd) {  in atmel_pwm_update_cdty()
248 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_update_cdty()
250 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);  in atmel_pwm_update_cdty()
253 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,  in atmel_pwm_update_cdty()
254 			    atmel_pwm->data->regs.duty_upd, cdty);  in atmel_pwm_update_cdty()
255 	atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);  in atmel_pwm_update_cdty()
259 				    struct pwm_device *pwm,  in atmel_pwm_set_cprd_cdty()  argument
264 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,  in atmel_pwm_set_cprd_cdty()
265 			    atmel_pwm->data->regs.duty, cdty);  in atmel_pwm_set_cprd_cdty()
266 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,  in atmel_pwm_set_cprd_cdty()
267 			    atmel_pwm->data->regs.period, cprd);  in atmel_pwm_set_cprd_cdty()
270 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,  in atmel_pwm_disable()  argument
276 	atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);  in atmel_pwm_disable()
278 	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);  in atmel_pwm_disable()
281 	 * Wait for the PWM channel disable operation to be effective before  in atmel_pwm_disable()
286 	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&  in atmel_pwm_disable()
291 		clk_disable(atmel_pwm->clk);  in atmel_pwm_disable()
294 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in atmel_pwm_apply()  argument
295 			   const struct pwm_state *state)  in atmel_pwm_apply()  argument
303 	pwm_get_state(pwm, &cstate);  in atmel_pwm_apply()
305 	if (state->enabled) {  in atmel_pwm_apply()
306 		unsigned long clkrate = clk_get_rate(atmel_pwm->clk);  in atmel_pwm_apply()
309 		    cstate.polarity == state->polarity &&  in atmel_pwm_apply()
310 		    cstate.period == state->period) {  in atmel_pwm_apply()
311 			u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_apply()
313 			cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,  in atmel_pwm_apply()
314 						  atmel_pwm->data->regs.period);  in atmel_pwm_apply()
317 			atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);  in atmel_pwm_apply()
318 			atmel_pwm_update_cdty(chip, pwm, cdty);  in atmel_pwm_apply()
322 		ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,  in atmel_pwm_apply()
325 			dev_err(chip->dev,  in atmel_pwm_apply()
330 		atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);  in atmel_pwm_apply()
333 			atmel_pwm_disable(chip, pwm, false);  in atmel_pwm_apply()
335 			ret = clk_enable(atmel_pwm->clk);  in atmel_pwm_apply()
337 				dev_err(chip->dev, "failed to enable clock\n");  in atmel_pwm_apply()
343 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_apply()
345 		if (state->polarity == PWM_POLARITY_NORMAL)  in atmel_pwm_apply()
349 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);  in atmel_pwm_apply()
350 		atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);  in atmel_pwm_apply()
351 		atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);  in atmel_pwm_apply()
353 		atmel_pwm_disable(chip, pwm, true);  in atmel_pwm_apply()
359 static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,  in atmel_pwm_get_state()  argument
360 				struct pwm_state *state)  in atmel_pwm_get_state()  argument
366 	cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_get_state()
368 	if (sr & (1 << pwm->hwpwm)) {  in atmel_pwm_get_state()
369 		unsigned long rate = clk_get_rate(atmel_pwm->clk);  in atmel_pwm_get_state()
375 		cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,  in atmel_pwm_get_state()
376 					  atmel_pwm->data->regs.period);  in atmel_pwm_get_state()
379 		state->period = DIV64_U64_ROUND_UP(tmp, rate);  in atmel_pwm_get_state()
382 		atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);  in atmel_pwm_get_state()
384 		cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,  in atmel_pwm_get_state()
385 					  atmel_pwm->data->regs.duty);  in atmel_pwm_get_state()
386 		tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;  in atmel_pwm_get_state()
388 		state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);  in atmel_pwm_get_state()
390 		state->enabled = true;  in atmel_pwm_get_state()
392 		state->enabled = false;  in atmel_pwm_get_state()
396 		state->polarity = PWM_POLARITY_INVERSED;  in atmel_pwm_get_state()
398 		state->polarity = PWM_POLARITY_NORMAL;  in atmel_pwm_get_state()
448 		.compatible = "atmel,at91sam9rl-pwm",
451 		.compatible = "atmel,sama5d3-pwm",
454 		.compatible = "atmel,sama5d2-pwm",
457 		.compatible = "microchip,sam9x60-pwm",
470 	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);  in atmel_pwm_probe()
472 		return -ENOMEM;  in atmel_pwm_probe()
474 	atmel_pwm->data = of_device_get_match_data(&pdev->dev);  in atmel_pwm_probe()
476 	atmel_pwm->update_pending = 0;  in atmel_pwm_probe()
477 	spin_lock_init(&atmel_pwm->lock);  in atmel_pwm_probe()
479 	atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);  in atmel_pwm_probe()
480 	if (IS_ERR(atmel_pwm->base))  in atmel_pwm_probe()
481 		return PTR_ERR(atmel_pwm->base);  in atmel_pwm_probe()
483 	atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);  in atmel_pwm_probe()
484 	if (IS_ERR(atmel_pwm->clk))  in atmel_pwm_probe()
485 		return PTR_ERR(atmel_pwm->clk);  in atmel_pwm_probe()
487 	ret = clk_prepare(atmel_pwm->clk);  in atmel_pwm_probe()
489 		dev_err(&pdev->dev, "failed to prepare PWM clock\n");  in atmel_pwm_probe()
493 	atmel_pwm->chip.dev = &pdev->dev;  in atmel_pwm_probe()
494 	atmel_pwm->chip.ops = &atmel_pwm_ops;  in atmel_pwm_probe()
495 	atmel_pwm->chip.npwm = 4;  in atmel_pwm_probe()
497 	ret = pwmchip_add(&atmel_pwm->chip);  in atmel_pwm_probe()
499 		dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);  in atmel_pwm_probe()
508 	clk_unprepare(atmel_pwm->clk);  in atmel_pwm_probe()
516 	pwmchip_remove(&atmel_pwm->chip);  in atmel_pwm_remove()
518 	clk_unprepare(atmel_pwm->clk);  in atmel_pwm_remove()
525 		.name = "atmel-pwm",
533 MODULE_ALIAS("platform:atmel-pwm");
535 MODULE_DESCRIPTION("Atmel PWM driver");