Lines Matching +full:0 +full:x01100000
25 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
26 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
28 #define PCI_VENDOR_ID_CELESTICA 0x18d4
29 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
61 #define OCP_CTRL_ENABLE BIT(0)
69 #define OCP_STATUS_IN_SYNC BIT(0)
72 #define OCP_SELECT_CLK_NONE 0
73 #define OCP_SELECT_CLK_REG 0xfe
91 #define TOD_CTRL_ENABLE BIT(0)
92 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
95 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
126 #define PPS_STATUS_FILTER_ERR BIT(0)
149 #define IRIG_M_CTRL_ENABLE BIT(0)
160 #define IRIG_S_CTRL_ENABLE BIT(0)
170 #define DCF_M_CTRL_ENABLE BIT(0)
180 #define DCF_S_CTRL_ENABLE BIT(0)
209 #define FREQ_STATUS_MASK GENMASK(23, 0)
267 #define OCP_CAP_BASIC BIT(0)
341 #define OCP_REQ_TIMESTAMP BIT(0)
387 { EEPROM_ENTRY(0x43, board_id) },
388 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
416 * 0: PPS (TS5)
438 .offset = 0x01000000, .size = 0x10000,
442 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
444 .index = 0,
451 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
460 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
469 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
478 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
488 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
496 OCP_EXT_RESOURCE(signal_out[0]),
497 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
506 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
515 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
524 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
533 .offset = 0x01030000, .size = 0x10000,
537 .offset = 0x01040000, .size = 0x10000,
541 .offset = 0x01050000, .size = 0x10000,
545 .offset = 0x01070000, .size = 0x10000,
549 .offset = 0x01080000, .size = 0x10000,
553 .offset = 0x01090000, .size = 0x10000,
557 .offset = 0x010A0000, .size = 0x10000,
561 .offset = 0x010B0000, .size = 0x10000,
565 .offset = 0x00020000, .size = 0x1000,
569 .offset = 0x00130000, .size = 0x1000,
573 .offset = 0x00140000, .size = 0x1000,
577 .offset = 0x00220000, .size = 0x1000,
581 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
589 { I2C_BOARD_INFO("24c02", 0x50) },
590 { I2C_BOARD_INFO("24mac402", 0x58),
598 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
602 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
606 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
610 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
614 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
616 .name = "xilinx_spi", .pci_offset = 0,
629 OCP_MEM_RESOURCE(freq_in[0]),
630 .offset = 0x01200000, .size = 0x10000,
634 .offset = 0x01210000, .size = 0x10000,
638 .offset = 0x01220000, .size = 0x10000,
642 .offset = 0x01230000, .size = 0x10000,
666 { .name = "NONE", .value = 0 },
673 { .name = "REGS", .value = 0xfe },
674 { .name = "EXT", .value = 0xff },
680 #define SMA_SELECT_MASK GENMASK(14, 0)
683 { .name = "10Mhz", .value = 0x0000 },
684 { .name = "PPS1", .value = 0x0001 },
685 { .name = "PPS2", .value = 0x0002 },
686 { .name = "TS1", .value = 0x0004 },
687 { .name = "TS2", .value = 0x0008 },
688 { .name = "IRIG", .value = 0x0010 },
689 { .name = "DCF", .value = 0x0020 },
690 { .name = "TS3", .value = 0x0040 },
691 { .name = "TS4", .value = 0x0080 },
692 { .name = "FREQ1", .value = 0x0100 },
693 { .name = "FREQ2", .value = 0x0200 },
694 { .name = "FREQ3", .value = 0x0400 },
695 { .name = "FREQ4", .value = 0x0800 },
701 { .name = "10Mhz", .value = 0x0000 },
702 { .name = "PHC", .value = 0x0001 },
703 { .name = "MAC", .value = 0x0002 },
704 { .name = "GNSS1", .value = 0x0004 },
705 { .name = "GNSS2", .value = 0x0008 },
706 { .name = "IRIG", .value = 0x0010 },
707 { .name = "DCF", .value = 0x0020 },
708 { .name = "GEN1", .value = 0x0040 },
709 { .name = "GEN2", .value = 0x0080 },
710 { .name = "GEN3", .value = 0x0100 },
711 { .name = "GEN4", .value = 0x0200 },
712 { .name = "GND", .value = 0x2000 },
713 { .name = "VCC", .value = 0x4000 },
754 for (i = 0; tbl[i].name; i++) in ptp_ocp_select_name_from_val()
766 for (i = 0; tbl[i].name; i++) { in ptp_ocp_select_val_from_name()
780 count = 0; in ptp_ocp_select_table_show()
781 for (i = 0; tbl[i].name; i++) in ptp_ocp_select_table_show()
801 for (i = 0; i < 100; i++) { in __ptp_ocp_gettime_locked()
820 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; in __ptp_ocp_gettime_locked()
870 return 0; in ptp_ocp_settime()
917 return 0; in ptp_ocp_adjtime()
920 sign = delta_ns < 0 ? BIT(31) : 0; in ptp_ocp_adjtime()
927 return 0; in ptp_ocp_adjtime()
933 if (scaled_ppm == 0) in ptp_ocp_null_adjfine()
934 return 0; in ptp_ocp_null_adjfine()
958 case 0: in ptp_ocp_enable()
984 case 0: in ptp_ocp_enable()
989 rq->perout.period.nsec != 0)) in ptp_ocp_enable()
991 return 0; in ptp_ocp_enable()
1028 return 0; in ptp_ocp_verify()
1030 /* channel 0 is 1PPS from PHC. in ptp_ocp_verify()
1069 iowrite32(0, &bp->reg->drift_ns); in __ptp_ocp_clear_drift_locked()
1116 bp->gnss_lost = 0; in ptp_ocp_watchdog()
1166 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */ in ptp_ocp_init_clock()
1167 iowrite32(0x2000, &bp->reg->servo_offset_p); in ptp_ocp_init_clock()
1168 iowrite32(0x1000, &bp->reg->servo_offset_i); in ptp_ocp_init_clock()
1169 iowrite32(0, &bp->reg->servo_drift_p); in ptp_ocp_init_clock()
1170 iowrite32(0, &bp->reg->servo_drift_i); in ptp_ocp_init_clock()
1176 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { in ptp_ocp_init_clock()
1191 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); in ptp_ocp_init_clock()
1195 return 0; in ptp_ocp_init_clock()
1247 return 0; in ptp_ocp_nvmem_match()
1252 return 0; in ptp_ocp_nvmem_match()
1346 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1347 offset = 0; in ptp_ocp_devlink_fw_image()
1356 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1365 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1369 crc = crc16(0xffff, &fw->data[offset], length); in ptp_ocp_devlink_fw_image()
1373 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1381 return 0; in ptp_ocp_devlink_fw_image()
1400 off = 0; in ptp_ocp_devlink_flash()
1445 NULL, 0, 0); in ptp_ocp_devlink_flash_update()
1450 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); in ptp_ocp_devlink_flash_update()
1478 return 0; in ptp_ocp_devlink_info_get()
1492 return 0; in ptp_ocp_devlink_info_get()
1513 start = pci_resource_start(bp->pdev, 0) + r->offset; in ptp_ocp_get_mem()
1541 start = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_register_spi()
1542 ptp_ocp_set_mem_resource(&res[0], start, r->size); in ptp_ocp_register_spi()
1557 return 0; in ptp_ocp_register_spi()
1568 start = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_i2c_bus()
1569 ptp_ocp_set_mem_resource(&res[0], start, r->size); in ptp_ocp_i2c_bus()
1591 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, in ptp_ocp_register_i2c()
1605 return 0; in ptp_ocp_register_i2c()
1625 iowrite32(0, ®->intr_mask); in ptp_ocp_signal_irq()
1626 iowrite32(0, ®->enable); in ptp_ocp_signal_irq()
1630 iowrite32(0, ®->intr); /* ack interrupt */ in ptp_ocp_signal_irq()
1644 return 0; in ptp_ocp_signal_set()
1671 return 0; in ptp_ocp_signal_set()
1683 return 0; in ptp_ocp_signal_from_perout()
1709 iowrite32(0, ®->intr_mask); in ptp_ocp_signal_enable()
1710 iowrite32(0, ®->enable); in ptp_ocp_signal_enable()
1713 return 0; in ptp_ocp_signal_enable()
1728 iowrite32(0, ®->repeat_count); in ptp_ocp_signal_enable()
1730 iowrite32(0, ®->intr); /* clear interrupt state */ in ptp_ocp_signal_enable()
1736 return 0; in ptp_ocp_signal_enable()
1753 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0) in ptp_ocp_ts_irq()
1789 if ((!!old_map ^ !!bp->pps_req_map) == 0) in ptp_ocp_ts_enable()
1790 return 0; in ptp_ocp_ts_enable()
1798 iowrite32(0, ®->intr_mask); in ptp_ocp_ts_enable()
1799 iowrite32(0, ®->enable); in ptp_ocp_ts_enable()
1802 return 0; in ptp_ocp_ts_enable()
1808 ext->info->enable(ext, ~0, false); in ptp_ocp_unregister_ext()
1843 return 0; in ptp_ocp_register_ext()
1859 memset(&uart, 0, sizeof(uart)); in ptp_ocp_serial_line()
1863 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_serial_line()
1878 if (port < 0) in ptp_ocp_register_serial()
1883 return 0; in ptp_ocp_register_serial()
1897 return 0; in ptp_ocp_register_mem()
1906 iowrite32(0, &bp->nmea_out->ctrl); /* disable */ in ptp_ocp_nmea_out_init()
1916 iowrite32(0, ®->enable); /* disable */ in _ptp_ocp_signal_init()
1928 for (i = 0; i < 4; i++) in ptp_ocp_signal_init()
1948 count = 0; in ptp_ocp_attr_group_add()
1949 for (i = 0; attr_tbl[i].cap; i++) in ptp_ocp_attr_group_add()
1958 count = 0; in ptp_ocp_attr_group_add()
1959 for (i = 0; attr_tbl[i].cap; i++) in ptp_ocp_attr_group_add()
1965 bp->attr_group[0] = NULL; in ptp_ocp_attr_group_add()
1980 ctrl |= enable ? bit : 0; in ptp_ocp_enable_fpga()
2016 ptp_ocp_irig_out(bp, val & 0x00100010); in __handle_signal_outputs()
2017 ptp_ocp_dcf_out(bp, val & 0x00200020); in __handle_signal_outputs()
2023 ptp_ocp_irig_in(bp, val & 0x00100010); in __handle_signal_inputs()
2024 ptp_ocp_dcf_in(bp, val & 0x00200020); in __handle_signal_inputs()
2040 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_get()
2042 return (ioread32(gpio) >> shift) & 0xffff; in ptp_ocp_sma_fb_get()
2053 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_set_output()
2055 mask = 0xffff << (16 - shift); in ptp_ocp_sma_fb_set_output()
2068 return 0; in ptp_ocp_sma_fb_set_output()
2079 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_set_inputs()
2081 mask = 0xffff << (16 - shift); in ptp_ocp_sma_fb_set_inputs()
2094 return 0; in ptp_ocp_sma_fb_set_inputs()
2104 bp->sma[0].mode = SMA_MODE_IN; in ptp_ocp_sma_fb_init()
2108 for (i = 0; i < 4; i++) in ptp_ocp_sma_fb_init()
2113 for (i = 0; i < 4; i++) { in ptp_ocp_sma_fb_init()
2124 if (reg == 0xffffffff) { in ptp_ocp_sma_fb_init()
2125 for (i = 0; i < 4; i++) in ptp_ocp_sma_fb_init()
2129 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT; in ptp_ocp_sma_fb_init()
2156 for (i = 0; i < 4; i++) { in ptp_ocp_fb_set_pins()
2164 return 0; in ptp_ocp_fb_set_pins()
2176 if ((version & 0xffff) == 0) { in ptp_ocp_fb_set_version()
2182 bp->fw_version = version & 0x7fff; in ptp_ocp_fb_set_version()
2243 int err = 0; in ptp_ocp_register_resources()
2284 for (i = 0; tbl[i].name; i++) { in ptp_ocp_show_inputs()
2290 if (!val && def_val >= 0) { in ptp_ocp_show_inputs()
2316 idx = 0; in sma_parse_inputs()
2317 dir = *mode == SMA_MODE_IN ? 0 : 1; in sma_parse_inputs()
2318 if (!strcasecmp("IN:", argv[0])) { in sma_parse_inputs()
2319 dir = 0; in sma_parse_inputs()
2322 if (!strcasecmp("OUT:", argv[0])) { in sma_parse_inputs()
2326 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT; in sma_parse_inputs()
2328 ret = 0; in sma_parse_inputs()
2331 if (ret < 0) in sma_parse_inputs()
2353 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val); in ptp_ocp_sma_show()
2364 return ptp_ocp_sma_show(bp, 1, buf, 0, 1); in sma1_show()
2380 return ptp_ocp_sma_show(bp, 3, buf, -1, 0); in sma3_show()
2400 if (val < 0) in ptp_ocp_sma_store()
2409 return 0; in ptp_ocp_sma_store()
2416 ptp_ocp_sma_set_output(bp, sma_nr, 0); in ptp_ocp_sma_store()
2418 ptp_ocp_sma_set_inputs(bp, sma_nr, 0); in ptp_ocp_sma_store()
2426 val = 0; in ptp_ocp_sma_store()
2490 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf); in available_sma_inputs_show()
2543 err = kstrtou64(argv[argc], 0, &s.phase); in signal_store()
2549 err = kstrtoint(argv[argc], 0, &s.duty); in signal_store()
2555 err = kstrtou64(argv[argc], 0, &s.period); in signal_store()
2567 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0); in signal_store()
2595 static EXT_ATTR_RW(signal, signal, 0);
2609 static EXT_ATTR_RO(signal, duty, 0);
2623 static EXT_ATTR_RO(signal, period, 0);
2637 static EXT_ATTR_RO(signal, phase, 0);
2652 static EXT_ATTR_RO(signal, polarity, 0);
2666 static EXT_ATTR_RO(signal, running, 0);
2682 static EXT_ATTR_RO(signal, start, 0);
2697 err = kstrtou32(buf, 0, &val); in seconds_store()
2700 if (val > 0xff) in seconds_store()
2704 val = (val << 8) | 0x1; in seconds_store()
2721 val = (val >> 8) & 0xff; in seconds_show()
2723 val = 0; in seconds_show()
2727 static EXT_ATTR_RW(freq, seconds, 0);
2747 return 0; in frequency_show()
2749 static EXT_ATTR_RO(freq, frequency, 0);
2799 err = kstrtou32(buf, 0, &val); in utc_tai_offset_store()
2827 err = kstrtou32(buf, 0, &val); in ts_window_adjust_store()
2844 val = (val >> 16) & 0x07; in irig_b_mode_show()
2859 err = kstrtou8(buf, 0, &val); in irig_b_mode_store()
2865 reg = ((val & 0x7) << 16); in irig_b_mode_store()
2868 iowrite32(0, &bp->irig_out->ctrl); /* disable */ in irig_b_mode_store()
2899 if (val < 0) in clock_source_store()
2969 u32 val = 0; in tod_correction_store()
2971 err = kstrtos32(buf, 0, &res); in tod_correction_store()
2974 if (res < 0) { in tod_correction_store()
3008 DEVICE_SIGNAL_GROUP(gen1, 0);
3028 DEVICE_FREQ_GROUP(freq1, 0);
3074 for (i = 0; i < 4; i++) { in gpio_input_map()
3077 if (map[i][0] & (1 << bit)) { in gpio_input_map()
3094 for (i = 0; i < 4; i++) { in gpio_output_map()
3143 val = (val >> 8) & 0xff; in _frequency_summary_show()
3189 memset(sma_val, 0xff, sizeof(sma_val)); in ptp_ocp_summary_show()
3194 sma_val[0][0] = reg & 0xffff; in ptp_ocp_summary_show()
3195 sma_val[1][0] = reg >> 16; in ptp_ocp_summary_show()
3198 sma_val[2][1] = reg & 0xffff; in ptp_ocp_summary_show()
3202 sma_val[2][0] = reg & 0xffff; in ptp_ocp_summary_show()
3203 sma_val[3][0] = reg >> 16; in ptp_ocp_summary_show()
3206 sma_val[0][1] = reg & 0xffff; in ptp_ocp_summary_show()
3212 sma_val[0][0], sma_val[0][1], buf); in ptp_ocp_summary_show()
3216 sma_val[1][0], sma_val[1][1], buf); in ptp_ocp_summary_show()
3220 sma_val[2][0], sma_val[2][1], buf); in ptp_ocp_summary_show()
3224 sma_val[3][0], sma_val[3][1], buf); in ptp_ocp_summary_show()
3280 for (i = 0; i < 4; i++) in ptp_ocp_summary_show()
3284 for (i = 0; i < 4; i++) in ptp_ocp_summary_show()
3332 if (val & 0x01) { in ptp_ocp_summary_show()
3333 gpio_input_map(src, bp, sma_val, 0, NULL); in ptp_ocp_summary_show()
3335 } else if (val & 0x02) { in ptp_ocp_summary_show()
3337 } else if (val & 0x04) { in ptp_ocp_summary_show()
3355 case 0: in ptp_ocp_summary_show()
3396 return 0; in ptp_ocp_summary_show()
3413 return 0; in ptp_ocp_tod_status_show()
3415 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val); in ptp_ocp_tod_status_show()
3417 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0; in ptp_ocp_tod_status_show()
3426 val >> 24, (val >> 16) & 0xff, val & 0xffff); in ptp_ocp_tod_status_show()
3429 seq_printf(s, "Status register: 0x%08X\n", val); in ptp_ocp_tod_status_show()
3437 seq_printf(s, "UTC status register: 0x%08X\n", val); in ptp_ocp_tod_status_show()
3439 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0); in ptp_ocp_tod_status_show()
3441 val & TOD_STATUS_LEAP_VALID ? 1 : 0, in ptp_ocp_tod_status_show()
3442 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0); in ptp_ocp_tod_status_show()
3447 return 0; in ptp_ocp_tod_status_show()
3501 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); in ptp_ocp_device_init()
3503 if (err < 0) { in ptp_ocp_device_init()
3532 return 0; in ptp_ocp_device_init()
3597 return 0; in ptp_ocp_complete()
3610 version >> 24, (version >> 16) & 0xff, version & 0xffff, in ptp_ocp_phc_info()
3688 for (i = 0; i < 4; i++) in ptp_ocp_detach()
3741 if (err < 0) { in ptp_ocp_probe()
3766 return 0; in ptp_ocp_probe()
3811 return 0; in ptp_ocp_i2c_notifier_call()
3815 return 0; in ptp_ocp_i2c_notifier_call()
3821 return 0; in ptp_ocp_i2c_notifier_call()
3830 return 0; in ptp_ocp_i2c_notifier_call()
3860 return 0; in ptp_ocp_init()