62 static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl,  in sunxi_mux_reg()  argument
68 	*reg   = bank * pctl->bank_mem_size + MUX_REGS_OFFSET +  in sunxi_mux_reg()
74 static void sunxi_data_reg(const struct sunxi_pinctrl *pctl,  in sunxi_data_reg()  argument
80 	*reg   = bank * pctl->bank_mem_size + DATA_REGS_OFFSET +  in sunxi_data_reg()
86 static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl,  in sunxi_dlevel_reg()  argument
90 	u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width;  in sunxi_dlevel_reg()
92 	*reg   = bank * pctl->bank_mem_size + DLEVEL_REGS_OFFSET +  in sunxi_dlevel_reg()
95 	*mask  = (BIT(pctl->dlevel_field_width) - 1) << *shift;  in sunxi_dlevel_reg()
98 static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl,  in sunxi_pull_reg()  argument
104 	*reg   = bank * pctl->bank_mem_size + pctl->pull_regs_offset +  in sunxi_pull_reg()
111 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)  in sunxi_pinctrl_find_group_by_name()  argument
115 	for (i = 0; i < pctl->ngroups; i++) {  in sunxi_pinctrl_find_group_by_name()
116 		struct sunxi_pinctrl_group *grp = pctl->groups + i;  in sunxi_pinctrl_find_group_by_name()
126 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_find_function_by_name()  argument
129 	struct sunxi_pinctrl_function *func = pctl->functions;  in sunxi_pinctrl_find_function_by_name()
132 	for (i = 0; i < pctl->nfunctions; i++) {  in sunxi_pinctrl_find_function_by_name()
144 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_desc_find_function_by_name()  argument
150 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_desc_find_function_by_name()
151 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_desc_find_function_by_name()
159 					func->variant & pctl->variant))  in sunxi_pinctrl_desc_find_function_by_name()
171 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_desc_find_function_by_pin()  argument
177 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_desc_find_function_by_pin()
178 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_desc_find_function_by_pin()
197 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pctrl_get_groups_count()  local
199 	return pctl->ngroups;  in sunxi_pctrl_get_groups_count()
205 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pctrl_get_group_name()  local
207 	return pctl->groups[group].name;  in sunxi_pctrl_get_group_name()
215 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pctrl_get_group_pins()  local
217 	*pins = (unsigned *)&pctl->groups[group].pin;  in sunxi_pctrl_get_group_pins()
393 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pctrl_dt_node_to_map()  local
405 		dev_err(pctl->dev, "missing function property in node %pOFn\n",  in sunxi_pctrl_dt_node_to_map()
412 		dev_err(pctl->dev, "missing pins property in node %pOFn\n",  in sunxi_pctrl_dt_node_to_map()
437 			sunxi_pinctrl_find_group_by_name(pctl, group);  in sunxi_pctrl_dt_node_to_map()
440 			dev_err(pctl->dev, "unknown pin %s", group);  in sunxi_pctrl_dt_node_to_map()
444 		if (!sunxi_pinctrl_desc_find_function_by_name(pctl,  in sunxi_pctrl_dt_node_to_map()
447 			dev_err(pctl->dev, "unsupported function %s on pin %s",  in sunxi_pctrl_dt_node_to_map()
515 static int sunxi_pconf_reg(const struct sunxi_pinctrl *pctl,  in sunxi_pconf_reg()  argument
521 		sunxi_dlevel_reg(pctl, pin, reg, shift, mask);  in sunxi_pconf_reg()
527 		sunxi_pull_reg(pctl, pin, reg, shift, mask);  in sunxi_pconf_reg()
540 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pconf_get()  local
546 	pin -= pctl->desc->pin_base;  in sunxi_pconf_get()
548 	ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);  in sunxi_pconf_get()
552 	val = (readl(pctl->membase + reg) & mask) >> shift;  in sunxi_pconf_get()
592 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pconf_group_get()  local
593 	struct sunxi_pinctrl_group *g = &pctl->groups[group];  in sunxi_pconf_group_get()
602 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pconf_set()  local
605 	pin -= pctl->desc->pin_base;  in sunxi_pconf_set()
616 		ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);  in sunxi_pconf_set()
652 		raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pconf_set()
653 		writel((readl(pctl->membase + reg) & ~mask) | val << shift,  in sunxi_pconf_set()
654 		       pctl->membase + reg);  in sunxi_pconf_set()
655 		raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pconf_set()
664 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pconf_group_set()  local
665 	struct sunxi_pinctrl_group *g = &pctl->groups[group];  in sunxi_pconf_group_set()
679 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_set_io_bias_cfg()  argument
688 	if (!pctl->desc->io_bias_cfg_variant)  in sunxi_pinctrl_set_io_bias_cfg()
699 	pin -= pctl->desc->pin_base;  in sunxi_pinctrl_set_io_bias_cfg()
702 	switch (pctl->desc->io_bias_cfg_variant) {  in sunxi_pinctrl_set_io_bias_cfg()
719 		reg = readl(pctl->membase + sunxi_grp_config_reg(pin));  in sunxi_pinctrl_set_io_bias_cfg()
721 		writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));  in sunxi_pinctrl_set_io_bias_cfg()
726 		raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_set_io_bias_cfg()
727 		reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG);  in sunxi_pinctrl_set_io_bias_cfg()
729 		writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG);  in sunxi_pinctrl_set_io_bias_cfg()
730 		raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_set_io_bias_cfg()
736 		raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_set_io_bias_cfg()
737 		reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);  in sunxi_pinctrl_set_io_bias_cfg()
739 		writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);  in sunxi_pinctrl_set_io_bias_cfg()
740 		raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_set_io_bias_cfg()
749 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_get_funcs_cnt()  local
751 	return pctl->nfunctions;  in sunxi_pmx_get_funcs_cnt()
757 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_get_func_name()  local
759 	return pctl->functions[function].name;  in sunxi_pmx_get_func_name()
767 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_get_func_groups()  local
769 	*groups = pctl->functions[function].groups;  in sunxi_pmx_get_func_groups()
770 	*num_groups = pctl->functions[function].ngroups;  in sunxi_pmx_get_func_groups()
779 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_set()  local
783 	pin -= pctl->desc->pin_base;  in sunxi_pmx_set()
784 	sunxi_mux_reg(pctl, pin, &reg, &shift, &mask);  in sunxi_pmx_set()
786 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pmx_set()
788 	writel((readl(pctl->membase + reg) & ~mask) | config << shift,  in sunxi_pmx_set()
789 	       pctl->membase + reg);  in sunxi_pmx_set()
791 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pmx_set()
798 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_set_mux()  local
799 	struct sunxi_pinctrl_group *g = pctl->groups + group;  in sunxi_pmx_set_mux()
800 	struct sunxi_pinctrl_function *func = pctl->functions + function;  in sunxi_pmx_set_mux()
802 		sunxi_pinctrl_desc_find_function_by_name(pctl,  in sunxi_pmx_set_mux()
820 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_gpio_set_direction()  local
829 	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);  in sunxi_pmx_gpio_set_direction()
840 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_request()  local
842 	unsigned short bank_offset = bank - pctl->desc->pin_base /  in sunxi_pmx_request()
844 	struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];  in sunxi_pmx_request()
855 	reg = regulator_get(pctl->dev, supply);  in sunxi_pmx_request()
857 		return dev_err_probe(pctl->dev, PTR_ERR(reg),  in sunxi_pmx_request()
863 		dev_err(pctl->dev,  in sunxi_pmx_request()
868 	sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);  in sunxi_pmx_request()
883 	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);  in sunxi_pmx_free()  local
885 	unsigned short bank_offset = bank - pctl->desc->pin_base /  in sunxi_pmx_free()
887 	struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];  in sunxi_pmx_free()
913 	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);  in sunxi_pinctrl_gpio_direction_input()  local
915 	return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,  in sunxi_pinctrl_gpio_direction_input()
921 	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);  in sunxi_pinctrl_gpio_get()  local
922 	bool set_mux = pctl->desc->irq_read_needs_mux &&  in sunxi_pinctrl_gpio_get()
927 	sunxi_data_reg(pctl, offset, &reg, &shift, &mask);  in sunxi_pinctrl_gpio_get()
930 		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);  in sunxi_pinctrl_gpio_get()
932 	val = (readl(pctl->membase + reg) & mask) >> shift;  in sunxi_pinctrl_gpio_get()
935 		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);  in sunxi_pinctrl_gpio_get()
943 	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);  in sunxi_pinctrl_gpio_set()  local
947 	sunxi_data_reg(pctl, offset, &reg, &shift, &mask);  in sunxi_pinctrl_gpio_set()
949 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_gpio_set()
951 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_gpio_set()
958 	writel(val, pctl->membase + reg);  in sunxi_pinctrl_gpio_set()
960 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_gpio_set()
966 	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);  in sunxi_pinctrl_gpio_direction_output()  local
969 	return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,  in sunxi_pinctrl_gpio_direction_output()
993 	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);  in sunxi_pinctrl_gpio_to_irq()  local
995 	unsigned pinnum = pctl->desc->pin_base + offset;  in sunxi_pinctrl_gpio_to_irq()
1001 	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");  in sunxi_pinctrl_gpio_to_irq()
1010 	return irq_find_mapping(pctl->domain, irqnum);  in sunxi_pinctrl_gpio_to_irq()
1015 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_request_resources()  local
1019 	func = sunxi_pinctrl_desc_find_function_by_pin(pctl,  in sunxi_pinctrl_irq_request_resources()
1020 					pctl->irq_array[d->hwirq], "irq");  in sunxi_pinctrl_irq_request_resources()
1024 	ret = gpiochip_lock_as_irq(pctl->chip,  in sunxi_pinctrl_irq_request_resources()
1025 			pctl->irq_array[d->hwirq] - pctl->desc->pin_base);  in sunxi_pinctrl_irq_request_resources()
1027 		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",  in sunxi_pinctrl_irq_request_resources()
1033 	sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);  in sunxi_pinctrl_irq_request_resources()
1040 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_release_resources()  local
1042 	gpiochip_unlock_as_irq(pctl->chip,  in sunxi_pinctrl_irq_release_resources()
1043 			      pctl->irq_array[d->hwirq] - pctl->desc->pin_base);  in sunxi_pinctrl_irq_release_resources()
1048 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_set_type()  local
1049 	u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);  in sunxi_pinctrl_irq_set_type()
1075 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_irq_set_type()
1084 	regval = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_set_type()
1086 	writel(regval | (mode << index), pctl->membase + reg);  in sunxi_pinctrl_irq_set_type()
1088 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_irq_set_type()
1095 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_ack()  local
1096 	u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);  in sunxi_pinctrl_irq_ack()
1100 	writel(1 << status_idx, pctl->membase + status_reg);  in sunxi_pinctrl_irq_ack()
1105 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_mask()  local
1106 	u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);  in sunxi_pinctrl_irq_mask()
1111 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_irq_mask()
1114 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_mask()
1115 	writel(val & ~(1 << idx), pctl->membase + reg);  in sunxi_pinctrl_irq_mask()
1117 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_irq_mask()
1122 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_unmask()  local
1123 	u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);  in sunxi_pinctrl_irq_unmask()
1128 	raw_spin_lock_irqsave(&pctl->lock, flags);  in sunxi_pinctrl_irq_unmask()
1131 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_unmask()
1132 	writel(val | (1 << idx), pctl->membase + reg);  in sunxi_pinctrl_irq_unmask()
1134 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in sunxi_pinctrl_irq_unmask()
1145 	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);  in sunxi_pinctrl_irq_set_wake()  local
1148 	return irq_set_irq_wake(pctl->irq[bank], on);  in sunxi_pinctrl_irq_set_wake()
1188 	struct sunxi_pinctrl *pctl = d->host_data;  in sunxi_pinctrl_irq_of_xlate()  local
1196 	pin = pctl->desc->pin_base + base + intspec[1];  in sunxi_pinctrl_irq_of_xlate()
1198 	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");  in sunxi_pinctrl_irq_of_xlate()
1216 	struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);  in sunxi_pinctrl_irq_handler()  local
1219 	for (bank = 0; bank < pctl->desc->irq_banks; bank++)  in sunxi_pinctrl_irq_handler()
1220 		if (irq == pctl->irq[bank])  in sunxi_pinctrl_irq_handler()
1223 	WARN_ON(bank == pctl->desc->irq_banks);  in sunxi_pinctrl_irq_handler()
1227 	reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);  in sunxi_pinctrl_irq_handler()
1228 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_handler()
1234 			generic_handle_domain_irq(pctl->domain,  in sunxi_pinctrl_irq_handler()
1241 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_add_function()  argument
1244 	struct sunxi_pinctrl_function *func = pctl->functions;  in sunxi_pinctrl_add_function()
1258 	pctl->nfunctions++;  in sunxi_pinctrl_add_function()
1265 	struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);  in sunxi_pinctrl_build_state()  local
1280 	pctl->groups = devm_kcalloc(&pdev->dev,  in sunxi_pinctrl_build_state()
1281 				    pctl->desc->npins, sizeof(*pctl->groups),  in sunxi_pinctrl_build_state()
1283 	if (!pctl->groups)  in sunxi_pinctrl_build_state()
1286 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_build_state()
1287 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_build_state()
1288 		struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;  in sunxi_pinctrl_build_state()
1290 		if (pin->variant && !(pctl->variant & pin->variant))  in sunxi_pinctrl_build_state()
1297 		pctl->ngroups++;  in sunxi_pinctrl_build_state()
1306 	pctl->functions = kcalloc(7 * pctl->ngroups + 4,  in sunxi_pinctrl_build_state()
1307 				  sizeof(*pctl->functions),  in sunxi_pinctrl_build_state()
1309 	if (!pctl->functions)  in sunxi_pinctrl_build_state()
1313 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_build_state()
1314 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_build_state()
1317 		if (pin->variant && !(pctl->variant & pin->variant))  in sunxi_pinctrl_build_state()
1321 			if (func->variant && !(pctl->variant & func->variant))  in sunxi_pinctrl_build_state()
1327 				pctl->irq_array[irqnum] = pin->pin.number;  in sunxi_pinctrl_build_state()
1330 			sunxi_pinctrl_add_function(pctl, func->name);  in sunxi_pinctrl_build_state()
1335 	ptr = krealloc(pctl->functions,  in sunxi_pinctrl_build_state()
1336 		       pctl->nfunctions * sizeof(*pctl->functions),  in sunxi_pinctrl_build_state()
1339 		kfree(pctl->functions);  in sunxi_pinctrl_build_state()
1340 		pctl->functions = NULL;  in sunxi_pinctrl_build_state()
1343 	pctl->functions = ptr;  in sunxi_pinctrl_build_state()
1345 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_build_state()
1346 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_build_state()
1349 		if (pin->variant && !(pctl->variant & pin->variant))  in sunxi_pinctrl_build_state()
1356 			if (func->variant && !(pctl->variant & func->variant))  in sunxi_pinctrl_build_state()
1359 			func_item = sunxi_pinctrl_find_function_by_name(pctl,  in sunxi_pinctrl_build_state()
1362 				kfree(pctl->functions);  in sunxi_pinctrl_build_state()
1373 					kfree(pctl->functions);  in sunxi_pinctrl_build_state()
1411 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,  in sunxi_pinctrl_setup_debounce()  argument
1428 	losc = devm_clk_get(pctl->dev, "losc");  in sunxi_pinctrl_setup_debounce()
1432 	hosc = devm_clk_get(pctl->dev, "hosc");  in sunxi_pinctrl_setup_debounce()
1436 	for (i = 0; i < pctl->desc->irq_banks; i++) {  in sunxi_pinctrl_setup_debounce()
1466 		       pctl->membase +  in sunxi_pinctrl_setup_debounce()
1467 		       sunxi_irq_debounce_reg_from_bank(pctl->desc, i));  in sunxi_pinctrl_setup_debounce()
1480 	struct sunxi_pinctrl *pctl;  in sunxi_pinctrl_init_with_variant()  local
1485 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);  in sunxi_pinctrl_init_with_variant()
1486 	if (!pctl)  in sunxi_pinctrl_init_with_variant()
1488 	platform_set_drvdata(pdev, pctl);  in sunxi_pinctrl_init_with_variant()
1490 	raw_spin_lock_init(&pctl->lock);  in sunxi_pinctrl_init_with_variant()
1492 	pctl->membase = devm_platform_ioremap_resource(pdev, 0);  in sunxi_pinctrl_init_with_variant()
1493 	if (IS_ERR(pctl->membase))  in sunxi_pinctrl_init_with_variant()
1494 		return PTR_ERR(pctl->membase);  in sunxi_pinctrl_init_with_variant()
1496 	pctl->dev = &pdev->dev;  in sunxi_pinctrl_init_with_variant()
1497 	pctl->desc = desc;  in sunxi_pinctrl_init_with_variant()
1498 	pctl->variant = variant;  in sunxi_pinctrl_init_with_variant()
1499 	if (pctl->variant >= PINCTRL_SUN20I_D1) {  in sunxi_pinctrl_init_with_variant()
1500 		pctl->bank_mem_size = D1_BANK_MEM_SIZE;  in sunxi_pinctrl_init_with_variant()
1501 		pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;  in sunxi_pinctrl_init_with_variant()
1502 		pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH;  in sunxi_pinctrl_init_with_variant()
1504 		pctl->bank_mem_size = BANK_MEM_SIZE;  in sunxi_pinctrl_init_with_variant()
1505 		pctl->pull_regs_offset = PULL_REGS_OFFSET;  in sunxi_pinctrl_init_with_variant()
1506 		pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH;  in sunxi_pinctrl_init_with_variant()
1509 	pctl->irq_array = devm_kcalloc(&pdev->dev,  in sunxi_pinctrl_init_with_variant()
1510 				       IRQ_PER_BANK * pctl->desc->irq_banks,  in sunxi_pinctrl_init_with_variant()
1511 				       sizeof(*pctl->irq_array),  in sunxi_pinctrl_init_with_variant()
1513 	if (!pctl->irq_array)  in sunxi_pinctrl_init_with_variant()
1523 			    pctl->desc->npins, sizeof(*pins),  in sunxi_pinctrl_init_with_variant()
1528 	for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_init_with_variant()
1529 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_init_with_variant()
1531 		if (pin->variant && !(pctl->variant & pin->variant))  in sunxi_pinctrl_init_with_variant()
1546 	pctrl_desc->npins = pctl->ngroups;  in sunxi_pinctrl_init_with_variant()
1560 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);  in sunxi_pinctrl_init_with_variant()
1561 	if (IS_ERR(pctl->pctl_dev)) {  in sunxi_pinctrl_init_with_variant()
1563 		return PTR_ERR(pctl->pctl_dev);  in sunxi_pinctrl_init_with_variant()
1566 	pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);  in sunxi_pinctrl_init_with_variant()
1567 	if (!pctl->chip)  in sunxi_pinctrl_init_with_variant()
1570 	last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;  in sunxi_pinctrl_init_with_variant()
1571 	pctl->chip->owner = THIS_MODULE;  in sunxi_pinctrl_init_with_variant()
1572 	pctl->chip->request = gpiochip_generic_request;  in sunxi_pinctrl_init_with_variant()
1573 	pctl->chip->free = gpiochip_generic_free;  in sunxi_pinctrl_init_with_variant()
1574 	pctl->chip->set_config = gpiochip_generic_config;  in sunxi_pinctrl_init_with_variant()
1575 	pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;  in sunxi_pinctrl_init_with_variant()
1576 	pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;  in sunxi_pinctrl_init_with_variant()
1577 	pctl->chip->get = sunxi_pinctrl_gpio_get;  in sunxi_pinctrl_init_with_variant()
1578 	pctl->chip->set = sunxi_pinctrl_gpio_set;  in sunxi_pinctrl_init_with_variant()
1579 	pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;  in sunxi_pinctrl_init_with_variant()
1580 	pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;  in sunxi_pinctrl_init_with_variant()
1581 	pctl->chip->of_gpio_n_cells = 3;  in sunxi_pinctrl_init_with_variant()
1582 	pctl->chip->can_sleep = false;  in sunxi_pinctrl_init_with_variant()
1583 	pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -  in sunxi_pinctrl_init_with_variant()
1584 			    pctl->desc->pin_base;  in sunxi_pinctrl_init_with_variant()
1585 	pctl->chip->label = dev_name(&pdev->dev);  in sunxi_pinctrl_init_with_variant()
1586 	pctl->chip->parent = &pdev->dev;  in sunxi_pinctrl_init_with_variant()
1587 	pctl->chip->base = pctl->desc->pin_base;  in sunxi_pinctrl_init_with_variant()
1589 	ret = gpiochip_add_data(pctl->chip, pctl);  in sunxi_pinctrl_init_with_variant()
1593 	for (i = 0; i < pctl->desc->npins; i++) {  in sunxi_pinctrl_init_with_variant()
1594 		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;  in sunxi_pinctrl_init_with_variant()
1596 		ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),  in sunxi_pinctrl_init_with_variant()
1597 					     pin->pin.number - pctl->desc->pin_base,  in sunxi_pinctrl_init_with_variant()
1614 	pctl->irq = devm_kcalloc(&pdev->dev,  in sunxi_pinctrl_init_with_variant()
1615 				 pctl->desc->irq_banks,  in sunxi_pinctrl_init_with_variant()
1616 				 sizeof(*pctl->irq),  in sunxi_pinctrl_init_with_variant()
1618 	if (!pctl->irq) {  in sunxi_pinctrl_init_with_variant()
1623 	for (i = 0; i < pctl->desc->irq_banks; i++) {  in sunxi_pinctrl_init_with_variant()
1624 		pctl->irq[i] = platform_get_irq(pdev, i);  in sunxi_pinctrl_init_with_variant()
1625 		if (pctl->irq[i] < 0) {  in sunxi_pinctrl_init_with_variant()
1626 			ret = pctl->irq[i];  in sunxi_pinctrl_init_with_variant()
1631 	pctl->domain = irq_domain_add_linear(node,  in sunxi_pinctrl_init_with_variant()
1632 					     pctl->desc->irq_banks * IRQ_PER_BANK,  in sunxi_pinctrl_init_with_variant()
1634 					     pctl);  in sunxi_pinctrl_init_with_variant()
1635 	if (!pctl->domain) {  in sunxi_pinctrl_init_with_variant()
1641 	for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {  in sunxi_pinctrl_init_with_variant()
1642 		int irqno = irq_create_mapping(pctl->domain, i);  in sunxi_pinctrl_init_with_variant()
1648 		irq_set_chip_data(irqno, pctl);  in sunxi_pinctrl_init_with_variant()
1651 	for (i = 0; i < pctl->desc->irq_banks; i++) {  in sunxi_pinctrl_init_with_variant()
1653 		writel(0, pctl->membase +  in sunxi_pinctrl_init_with_variant()
1654 			  sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));  in sunxi_pinctrl_init_with_variant()
1656 		       pctl->membase +  in sunxi_pinctrl_init_with_variant()
1657 		       sunxi_irq_status_reg_from_bank(pctl->desc, i));  in sunxi_pinctrl_init_with_variant()
1659 		irq_set_chained_handler_and_data(pctl->irq[i],  in sunxi_pinctrl_init_with_variant()
1661 						 pctl);  in sunxi_pinctrl_init_with_variant()
1664 	sunxi_pinctrl_setup_debounce(pctl, node);  in sunxi_pinctrl_init_with_variant()
1673 	gpiochip_remove(pctl->chip);  in sunxi_pinctrl_init_with_variant()