Lines Matching +full:pctl +full:- +full:regmap
1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/regmap.h>
34 #include "../pinctrl-utils.h"
35 #include "pinctrl-stm32.h"
113 struct regmap *regmap; member
148 return function - 1; in stm32_gpio_get_alt()
159 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
160 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
166 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
168 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
169 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
175 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
176 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
182 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; in stm32_gpio_backup_speed()
183 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; in stm32_gpio_backup_speed()
189 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; in stm32_gpio_backup_bias()
190 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; in stm32_gpio_backup_bias()
203 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
209 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request() local
211 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
213 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); in stm32_gpio_request()
215 dev_err(pctl->dev, "pin %d not in range.\n", pin); in stm32_gpio_request()
216 return -EINVAL; in stm32_gpio_request()
219 return pinctrl_gpio_request(chip->base + offset); in stm32_gpio_request()
224 pinctrl_gpio_free(chip->base + offset); in stm32_gpio_free()
231 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
243 return pinctrl_gpio_direction_input(chip->base + offset); in stm32_gpio_direction_input()
252 pinctrl_gpio_direction_output(chip->base + offset); in stm32_gpio_direction_output()
263 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
284 ret = -EINVAL; in stm32_gpio_get_direction()
294 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_init_valid_mask() local
301 if (bank->secure_control) { in stm32_gpio_init_valid_mask()
303 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); in stm32_gpio_init_valid_mask()
308 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); in stm32_gpio_init_valid_mask()
331 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_irq_trigger()
335 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) in stm32_gpio_irq_trigger()
339 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); in stm32_gpio_irq_trigger()
340 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || in stm32_gpio_irq_trigger()
341 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) in stm32_gpio_irq_trigger()
353 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_set_type()
369 return -EINVAL; in stm32_gpio_set_type()
372 bank->irq_type[d->hwirq] = type; in stm32_gpio_set_type()
379 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources()
380 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources() local
383 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
387 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
389 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", in stm32_gpio_irq_request_resources()
390 irq_data->hwirq); in stm32_gpio_irq_request_resources()
399 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources()
401 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
427 if ((fwspec->param_count != 2) || in stm32_gpio_domain_translate()
428 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) in stm32_gpio_domain_translate()
429 return -EINVAL; in stm32_gpio_domain_translate()
431 *hwirq = fwspec->param[0]; in stm32_gpio_domain_translate()
432 *type = fwspec->param[1]; in stm32_gpio_domain_translate()
439 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate()
440 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate() local
443 if (pctl->hwlock) { in stm32_gpio_domain_activate()
444 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_gpio_domain_activate()
447 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_gpio_domain_activate()
452 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
454 if (pctl->hwlock) in stm32_gpio_domain_activate()
455 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_gpio_domain_activate()
464 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc()
467 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_alloc() local
468 irq_hw_number_t hwirq = fwspec->param[0]; in stm32_gpio_domain_alloc()
476 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
478 if (pctl->irqmux_map & BIT(hwirq)) { in stm32_gpio_domain_alloc()
479 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); in stm32_gpio_domain_alloc()
480 ret = -EBUSY; in stm32_gpio_domain_alloc()
482 pctl->irqmux_map |= BIT(hwirq); in stm32_gpio_domain_alloc()
485 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
489 parent_fwspec.fwnode = d->parent->fwnode; in stm32_gpio_domain_alloc()
491 parent_fwspec.param[0] = fwspec->param[0]; in stm32_gpio_domain_alloc()
492 parent_fwspec.param[1] = fwspec->param[1]; in stm32_gpio_domain_alloc()
503 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_free()
504 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_free() local
506 unsigned long flags, hwirq = irq_data->hwirq; in stm32_gpio_domain_free()
510 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
511 pctl->irqmux_map &= ~BIT(hwirq); in stm32_gpio_domain_free()
512 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
524 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) in stm32_pctrl_find_group_by_pin() argument
528 for (i = 0; i < pctl->ngroups; i++) { in stm32_pctrl_find_group_by_pin()
529 struct stm32_pinctrl_group *grp = pctl->groups + i; in stm32_pctrl_find_group_by_pin()
531 if (grp->pin == pin) in stm32_pctrl_find_group_by_pin()
538 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, in stm32_pctrl_is_function_valid() argument
543 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_is_function_valid()
544 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_is_function_valid()
545 const struct stm32_desc_function *func = pin->functions; in stm32_pctrl_is_function_valid()
547 if (pin->pin.number != pin_num) in stm32_pctrl_is_function_valid()
551 if (func->num == fnum) in stm32_pctrl_is_function_valid()
559 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); in stm32_pctrl_is_function_valid()
564 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, in stm32_pctrl_dt_node_to_map_func() argument
570 return -ENOSPC; in stm32_pctrl_dt_node_to_map_func()
573 (*map)[*num_maps].data.mux.group = grp->name; in stm32_pctrl_dt_node_to_map_func()
575 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) in stm32_pctrl_dt_node_to_map_func()
576 return -EINVAL; in stm32_pctrl_dt_node_to_map_func()
590 struct stm32_pinctrl *pctl; in stm32_pctrl_dt_subnode_to_map() local
600 pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_dt_subnode_to_map()
604 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", in stm32_pctrl_dt_subnode_to_map()
606 return -EINVAL; in stm32_pctrl_dt_subnode_to_map()
617 num_pins = pins->length / sizeof(u32); in stm32_pctrl_dt_subnode_to_map()
626 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
646 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { in stm32_pctrl_dt_subnode_to_map()
647 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
651 grp = stm32_pctrl_find_group_by_pin(pctl, pin); in stm32_pctrl_dt_subnode_to_map()
653 dev_err(pctl->dev, "unable to match pin %d to group\n", in stm32_pctrl_dt_subnode_to_map()
655 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
659 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, in stm32_pctrl_dt_subnode_to_map()
666 reserved_maps, num_maps, grp->name, in stm32_pctrl_dt_subnode_to_map()
706 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_groups_count() local
708 return pctl->ngroups; in stm32_pctrl_get_groups_count()
714 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_group_name() local
716 return pctl->groups[group].name; in stm32_pctrl_get_group_name()
724 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_group_pins() local
726 *pins = (unsigned *)&pctl->groups[group].pin; in stm32_pctrl_get_group_pins()
759 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_get_func_groups() local
761 *groups = pctl->grp_names; in stm32_pmx_get_func_groups()
762 *num_groups = pctl->ngroups; in stm32_pmx_get_func_groups()
770 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode() local
777 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
779 if (pctl->hwlock) { in stm32_pmx_set_mode()
780 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pmx_set_mode()
783 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pmx_set_mode()
788 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
791 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
793 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
796 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
798 if (pctl->hwlock) in stm32_pmx_set_mode()
799 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pmx_set_mode()
804 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
817 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
819 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
823 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
827 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
835 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_set_mux() local
836 struct stm32_pinctrl_group *g = pctl->groups + group; in stm32_pmx_set_mux()
842 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); in stm32_pmx_set_mux()
844 return -EINVAL; in stm32_pmx_set_mux()
846 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); in stm32_pmx_set_mux()
848 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_set_mux()
849 return -EINVAL; in stm32_pmx_set_mux()
852 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
853 pin = stm32_gpio_pin(g->pin); in stm32_pmx_set_mux()
865 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction()
873 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_request() local
878 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_request()
879 return -EINVAL; in stm32_pmx_request()
882 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) { in stm32_pmx_request()
883 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); in stm32_pmx_request()
884 return -EACCES; in stm32_pmx_request()
905 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving() local
910 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
912 if (pctl->hwlock) { in stm32_pconf_set_driving()
913 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_driving()
916 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_driving()
921 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
924 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
926 if (pctl->hwlock) in stm32_pconf_set_driving()
927 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_driving()
932 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
943 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
945 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
948 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
956 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed() local
961 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
963 if (pctl->hwlock) { in stm32_pconf_set_speed()
964 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_speed()
967 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_speed()
972 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
975 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
977 if (pctl->hwlock) in stm32_pconf_set_speed()
978 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_speed()
983 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
994 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
996 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
999 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
1007 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias() local
1012 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
1014 if (pctl->hwlock) { in stm32_pconf_set_bias()
1015 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_bias()
1018 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_bias()
1023 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1026 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1028 if (pctl->hwlock) in stm32_pconf_set_bias()
1029 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_bias()
1034 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
1045 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
1047 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
1050 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
1061 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
1064 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
1067 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
1070 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
1079 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_parse_conf() local
1086 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pconf_parse_conf()
1087 return -EINVAL; in stm32_pconf_parse_conf()
1090 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
1093 if (!gpiochip_line_is_valid(range->gc, offset)) { in stm32_pconf_parse_conf()
1094 dev_warn(pctl->dev, "Can't access gpio %d\n", pin); in stm32_pconf_parse_conf()
1095 return -EACCES; in stm32_pconf_parse_conf()
1122 ret = -ENOTSUPP; in stm32_pconf_parse_conf()
1132 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_group_get() local
1134 *config = pctl->groups[group].config; in stm32_pconf_group_get()
1142 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_group_set() local
1143 struct stm32_pinctrl_group *g = &pctl->groups[group]; in stm32_pconf_group_set()
1147 mutex_lock(&pctldev->mutex); in stm32_pconf_group_set()
1148 ret = stm32_pconf_parse_conf(pctldev, g->pin, in stm32_pconf_group_set()
1151 mutex_unlock(&pctldev->mutex); in stm32_pconf_group_set()
1155 g->config = configs[i]; in stm32_pconf_group_set()
1178 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl, in stm32_pconf_get_pin_desc_by_pin_number() argument
1181 struct stm32_desc_pin *pins = pctl->pins; in stm32_pconf_get_pin_desc_by_pin_number()
1184 for (i = 0; i < pctl->npins; i++) { in stm32_pconf_get_pin_desc_by_pin_number()
1185 if (pins->pin.number == pin_number) in stm32_pconf_get_pin_desc_by_pin_number()
1196 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_dbg_show() local
1214 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
1217 if (!gpiochip_line_is_valid(range->gc, offset)) { in stm32_pconf_dbg_show()
1231 seq_printf(s, "- %s - %s", in stm32_pconf_dbg_show()
1241 seq_printf(s, "- %s - %s - %s - %s %s", in stm32_pconf_dbg_show()
1252 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin); in stm32_pconf_dbg_show()
1256 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt, in stm32_pconf_dbg_show()
1257 pin_desc->functions[alt + 1].name, in stm32_pconf_dbg_show()
1276 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) in stm32_gpiolib_register_bank() argument
1278 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank()
1280 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
1282 struct device *dev = pctl->dev; in stm32_gpiolib_register_bank()
1287 if (!IS_ERR(bank->rstc)) in stm32_gpiolib_register_bank()
1288 reset_control_deassert(bank->rstc); in stm32_gpiolib_register_bank()
1291 return -ENODEV; in stm32_gpiolib_register_bank()
1293 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
1294 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
1295 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
1297 err = clk_prepare_enable(bank->clk); in stm32_gpiolib_register_bank()
1303 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1305 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1307 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) { in stm32_gpiolib_register_bank()
1309 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1313 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) in stm32_gpiolib_register_bank()
1316 bank_nr = pctl->nbanks; in stm32_gpiolib_register_bank()
1317 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1318 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1319 range->id = bank_nr; in stm32_gpiolib_register_bank()
1320 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1321 range->base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1322 range->npins = npins; in stm32_gpiolib_register_bank()
1323 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1324 pinctrl_add_gpio_range(pctl->pctl_dev, in stm32_gpiolib_register_bank()
1325 &pctl->banks[bank_nr].range); in stm32_gpiolib_register_bank()
1328 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) in stm32_gpiolib_register_bank()
1331 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1333 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1334 bank->gpio_chip.fwnode = fwnode; in stm32_gpiolib_register_bank()
1335 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1336 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1337 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1338 bank->secure_control = pctl->match_data->secure_control; in stm32_gpiolib_register_bank()
1339 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1341 if (pctl->domain) { in stm32_gpiolib_register_bank()
1343 bank->fwnode = fwnode; in stm32_gpiolib_register_bank()
1345 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, in stm32_gpiolib_register_bank()
1346 bank->fwnode, &stm32_gpio_domain_ops, in stm32_gpiolib_register_bank()
1349 if (!bank->domain) { in stm32_gpiolib_register_bank()
1350 err = -ENODEV; in stm32_gpiolib_register_bank()
1355 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1361 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1365 clk_disable_unprepare(bank->clk); in stm32_gpiolib_register_bank()
1371 struct device_node *np = pdev->dev.of_node; in stm32_pctrl_get_irq_domain()
1375 if (!of_find_property(np, "interrupt-parent", NULL)) in stm32_pctrl_get_irq_domain()
1380 return ERR_PTR(-ENXIO); in stm32_pctrl_get_irq_domain()
1385 return ERR_PTR(-EPROBE_DEFER); in stm32_pctrl_get_irq_domain()
1391 struct stm32_pinctrl *pctl) in stm32_pctrl_dt_setup_irq() argument
1393 struct device_node *np = pdev->dev.of_node; in stm32_pctrl_dt_setup_irq()
1394 struct device *dev = &pdev->dev; in stm32_pctrl_dt_setup_irq()
1395 struct regmap *rm; in stm32_pctrl_dt_setup_irq()
1399 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in stm32_pctrl_dt_setup_irq()
1400 if (IS_ERR(pctl->regmap)) in stm32_pctrl_dt_setup_irq()
1401 return PTR_ERR(pctl->regmap); in stm32_pctrl_dt_setup_irq()
1403 rm = pctl->regmap; in stm32_pctrl_dt_setup_irq()
1420 mux.msb = mux.lsb + mask_width - 1; in stm32_pctrl_dt_setup_irq()
1425 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); in stm32_pctrl_dt_setup_irq()
1426 if (IS_ERR(pctl->irqmux[i])) in stm32_pctrl_dt_setup_irq()
1427 return PTR_ERR(pctl->irqmux[i]); in stm32_pctrl_dt_setup_irq()
1435 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); in stm32_pctrl_build_state() local
1438 pctl->ngroups = pctl->npins; in stm32_pctrl_build_state()
1441 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1442 sizeof(*pctl->groups), GFP_KERNEL); in stm32_pctrl_build_state()
1443 if (!pctl->groups) in stm32_pctrl_build_state()
1444 return -ENOMEM; in stm32_pctrl_build_state()
1447 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1448 sizeof(*pctl->grp_names), GFP_KERNEL); in stm32_pctrl_build_state()
1449 if (!pctl->grp_names) in stm32_pctrl_build_state()
1450 return -ENOMEM; in stm32_pctrl_build_state()
1452 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_build_state()
1453 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_build_state()
1454 struct stm32_pinctrl_group *group = pctl->groups + i; in stm32_pctrl_build_state()
1456 group->name = pin->pin.name; in stm32_pctrl_build_state()
1457 group->pin = pin->pin.number; in stm32_pctrl_build_state()
1458 pctl->grp_names[i] = pin->pin.name; in stm32_pctrl_build_state()
1464 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, in stm32_pctrl_create_pins_tab() argument
1470 for (i = 0; i < pctl->match_data->npins; i++) { in stm32_pctrl_create_pins_tab()
1471 p = pctl->match_data->pins + i; in stm32_pctrl_create_pins_tab()
1472 if (pctl->pkg && !(pctl->pkg & p->pkg)) in stm32_pctrl_create_pins_tab()
1474 pins->pin = p->pin; in stm32_pctrl_create_pins_tab()
1475 memcpy((struct stm32_desc_pin *)pins->functions, p->functions, in stm32_pctrl_create_pins_tab()
1481 pctl->npins = nb_pins_available; in stm32_pctrl_create_pins_tab()
1490 struct device *dev = &pdev->dev; in stm32_pctl_probe()
1491 struct stm32_pinctrl *pctl; in stm32_pctl_probe() local
1498 return -EINVAL; in stm32_pctl_probe()
1500 if (!device_property_present(dev, "pins-are-numbered")) { in stm32_pctl_probe()
1501 dev_err(dev, "only support pins-are-numbered format\n"); in stm32_pctl_probe()
1502 return -EINVAL; in stm32_pctl_probe()
1505 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); in stm32_pctl_probe()
1506 if (!pctl) in stm32_pctl_probe()
1507 return -ENOMEM; in stm32_pctl_probe()
1509 platform_set_drvdata(pdev, pctl); in stm32_pctl_probe()
1512 pctl->domain = stm32_pctrl_get_irq_domain(pdev); in stm32_pctl_probe()
1513 if (IS_ERR(pctl->domain)) in stm32_pctl_probe()
1514 return PTR_ERR(pctl->domain); in stm32_pctl_probe()
1515 if (!pctl->domain) in stm32_pctl_probe()
1519 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); in stm32_pctl_probe()
1521 if (hwlock_id == -EPROBE_DEFER) in stm32_pctl_probe()
1524 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); in stm32_pctl_probe()
1527 spin_lock_init(&pctl->irqmux_lock); in stm32_pctl_probe()
1529 pctl->dev = dev; in stm32_pctl_probe()
1530 pctl->match_data = match_data; in stm32_pctl_probe()
1533 if (!device_property_read_u32(dev, "st,package", &pctl->pkg)) in stm32_pctl_probe()
1534 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); in stm32_pctl_probe()
1536 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, in stm32_pctl_probe()
1537 sizeof(*pctl->pins), GFP_KERNEL); in stm32_pctl_probe()
1538 if (!pctl->pins) in stm32_pctl_probe()
1539 return -ENOMEM; in stm32_pctl_probe()
1541 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); in stm32_pctl_probe()
1548 return -EINVAL; in stm32_pctl_probe()
1551 if (pctl->domain) { in stm32_pctl_probe()
1552 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); in stm32_pctl_probe()
1557 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), in stm32_pctl_probe()
1560 return -ENOMEM; in stm32_pctl_probe()
1562 for (i = 0; i < pctl->npins; i++) in stm32_pctl_probe()
1563 pins[i] = pctl->pins[i].pin; in stm32_pctl_probe()
1565 pctl->pctl_desc.name = dev_name(&pdev->dev); in stm32_pctl_probe()
1566 pctl->pctl_desc.owner = THIS_MODULE; in stm32_pctl_probe()
1567 pctl->pctl_desc.pins = pins; in stm32_pctl_probe()
1568 pctl->pctl_desc.npins = pctl->npins; in stm32_pctl_probe()
1569 pctl->pctl_desc.link_consumers = true; in stm32_pctl_probe()
1570 pctl->pctl_desc.confops = &stm32_pconf_ops; in stm32_pctl_probe()
1571 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; in stm32_pctl_probe()
1572 pctl->pctl_desc.pmxops = &stm32_pmx_ops; in stm32_pctl_probe()
1573 pctl->dev = &pdev->dev; in stm32_pctl_probe()
1575 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, in stm32_pctl_probe()
1576 pctl); in stm32_pctl_probe()
1578 if (IS_ERR(pctl->pctl_dev)) { in stm32_pctl_probe()
1579 dev_err(&pdev->dev, "Failed pinctrl registration\n"); in stm32_pctl_probe()
1580 return PTR_ERR(pctl->pctl_dev); in stm32_pctl_probe()
1586 return -EINVAL; in stm32_pctl_probe()
1588 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), in stm32_pctl_probe()
1590 if (!pctl->banks) in stm32_pctl_probe()
1591 return -ENOMEM; in stm32_pctl_probe()
1595 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe()
1598 bank->rstc = of_reset_control_get_exclusive(np, NULL); in stm32_pctl_probe()
1599 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { in stm32_pctl_probe()
1601 return -EPROBE_DEFER; in stm32_pctl_probe()
1604 bank->clk = of_clk_get_by_name(np, NULL); in stm32_pctl_probe()
1605 if (IS_ERR(bank->clk)) { in stm32_pctl_probe()
1607 return dev_err_probe(dev, PTR_ERR(bank->clk), in stm32_pctl_probe()
1614 ret = stm32_gpiolib_register_bank(pctl, child); in stm32_pctl_probe()
1618 for (i = 0; i < pctl->nbanks; i++) in stm32_pctl_probe()
1619 clk_disable_unprepare(pctl->banks[i].clk); in stm32_pctl_probe()
1624 pctl->nbanks++; in stm32_pctl_probe()
1633 struct stm32_pinctrl *pctl, u32 pin) in stm32_pinctrl_restore_gpio_regs() argument
1635 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1642 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1646 if (!gpiochip_line_is_valid(range->gc, offset)) in stm32_pinctrl_restore_gpio_regs()
1649 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); in stm32_pinctrl_restore_gpio_regs()
1651 if (!desc || (!pin_is_irq && !desc->gpio_owner)) in stm32_pinctrl_restore_gpio_regs()
1654 bank = gpiochip_get_data(range->gc); in stm32_pinctrl_restore_gpio_regs()
1656 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; in stm32_pinctrl_restore_gpio_regs()
1658 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; in stm32_pinctrl_restore_gpio_regs()
1666 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); in stm32_pinctrl_restore_gpio_regs()
1671 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); in stm32_pinctrl_restore_gpio_regs()
1677 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; in stm32_pinctrl_restore_gpio_regs()
1683 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; in stm32_pinctrl_restore_gpio_regs()
1690 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()
1697 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); in stm32_pinctrl_suspend() local
1700 for (i = 0; i < pctl->nbanks; i++) in stm32_pinctrl_suspend()
1701 clk_disable(pctl->banks[i].clk); in stm32_pinctrl_suspend()
1708 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); in stm32_pinctrl_resume() local
1709 struct stm32_pinctrl_group *g = pctl->groups; in stm32_pinctrl_resume()
1712 for (i = 0; i < pctl->nbanks; i++) in stm32_pinctrl_resume()
1713 clk_enable(pctl->banks[i].clk); in stm32_pinctrl_resume()
1715 for (i = 0; i < pctl->ngroups; i++, g++) in stm32_pinctrl_resume()
1716 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); in stm32_pinctrl_resume()