156 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,  in stm32_gpio_backup_value()  argument
159 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);  in stm32_gpio_backup_value()
160 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;  in stm32_gpio_backup_value()
163 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_mode()  argument
166 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |  in stm32_gpio_backup_mode()
168 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;  in stm32_gpio_backup_mode()
169 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;  in stm32_gpio_backup_mode()
172 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_driving()  argument
175 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);  in stm32_gpio_backup_driving()
176 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;  in stm32_gpio_backup_driving()
179 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_speed()  argument
182 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;  in stm32_gpio_backup_speed()
183 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;  in stm32_gpio_backup_speed()
186 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_bias()  argument
189 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;  in stm32_gpio_backup_bias()
190 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;  in stm32_gpio_backup_bias()
195 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,  in __stm32_gpio_set()  argument
198 	stm32_gpio_backup_value(bank, offset, value);  in __stm32_gpio_set()
203 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);  in __stm32_gpio_set()
208 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_request()  local
209 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_request()
211 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);  in stm32_gpio_request()
229 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_get()  local
231 	return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));  in stm32_gpio_get()
236 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_set()  local
238 	__stm32_gpio_set(bank, offset, value);  in stm32_gpio_set()
249 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_direction_output()  local
251 	__stm32_gpio_set(bank, offset, value);  in stm32_gpio_direction_output()
260 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_to_irq()  local
263 	fwspec.fwnode = bank->fwnode;  in stm32_gpio_to_irq()
273 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_get_direction()  local
278 	stm32_pmx_get_mode(bank, pin, &mode, &alt);  in stm32_gpio_get_direction()
293 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_init_valid_mask()  local
294 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_init_valid_mask()
301 	if (bank->secure_control) {  in stm32_gpio_init_valid_mask()
303 		sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);  in stm32_gpio_init_valid_mask()
308 				dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);  in stm32_gpio_init_valid_mask()
331 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_irq_trigger()  local
335 	if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))  in stm32_gpio_irq_trigger()
339 	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);  in stm32_gpio_irq_trigger()
340 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||  in stm32_gpio_irq_trigger()
341 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))  in stm32_gpio_irq_trigger()
353 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_set_type()  local
372 	bank->irq_type[d->hwirq] = type;  in stm32_gpio_set_type()
379 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_request_resources()  local
380 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_irq_request_resources()
383 	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
387 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
399 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_release_resources()  local
401 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_release_resources()
439 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_activate()  local
440 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_activate()
452 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);  in stm32_gpio_domain_activate()
464 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_alloc()  local
467 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_alloc()
495 				      bank);  in stm32_gpio_domain_alloc()
503 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_free()  local
504 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_free()
767 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,  in stm32_pmx_set_mode()  argument
770 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pmx_set_mode()
777 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_set_mode()
788 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_set_mode()
791 	writel_relaxed(val, bank->base + alt_offset);  in stm32_pmx_set_mode()
793 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
796 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
801 	stm32_gpio_backup_mode(bank, pin, mode, alt);  in stm32_pmx_set_mode()
804 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_set_mode()
809 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,  in stm32_pmx_get_mode()  argument
817 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_get_mode()
819 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_get_mode()
823 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_get_mode()
827 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_get_mode()
838 	struct stm32_gpio_bank *bank;  in stm32_pmx_set_mux()  local
852 	bank = gpiochip_get_data(range->gc);  in stm32_pmx_set_mux()
858 	return stm32_pmx_set_mode(bank, pin, mode, alt);  in stm32_pmx_set_mux()
865 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);  in stm32_pmx_gpio_set_direction()  local
868 	return stm32_pmx_set_mode(bank, pin, !input, 0);  in stm32_pmx_gpio_set_direction()
902 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,  in stm32_pconf_set_driving()  argument
905 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_driving()
910 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_driving()
921 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
924 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
929 	stm32_gpio_backup_driving(bank, offset, drive);  in stm32_pconf_set_driving()
932 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_driving()
937 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,  in stm32_pconf_get_driving()  argument
943 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_driving()
945 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_get_driving()
948 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_driving()
953 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,  in stm32_pconf_set_speed()  argument
956 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_speed()
961 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_speed()
972 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
975 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
980 	stm32_gpio_backup_speed(bank, offset, speed);  in stm32_pconf_set_speed()
983 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_speed()
988 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,  in stm32_pconf_get_speed()  argument
994 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_speed()
996 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_get_speed()
999 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_speed()
1004 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,  in stm32_pconf_set_bias()  argument
1007 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_bias()
1012 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_bias()
1023 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
1026 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
1031 	stm32_gpio_backup_bias(bank, offset, bias);  in stm32_pconf_set_bias()
1034 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_bias()
1039 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,  in stm32_pconf_get_bias()  argument
1045 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_bias()
1047 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_get_bias()
1050 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_bias()
1055 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,  in stm32_pconf_get()  argument
1061 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get()
1064 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &  in stm32_pconf_get()
1067 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &  in stm32_pconf_get()
1070 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get()
1081 	struct stm32_gpio_bank *bank;  in stm32_pconf_parse_conf()  local
1090 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_parse_conf()
1100 		ret = stm32_pconf_set_driving(bank, offset, 0);  in stm32_pconf_parse_conf()
1103 		ret = stm32_pconf_set_driving(bank, offset, 1);  in stm32_pconf_parse_conf()
1106 		ret = stm32_pconf_set_speed(bank, offset, arg);  in stm32_pconf_parse_conf()
1109 		ret = stm32_pconf_set_bias(bank, offset, 0);  in stm32_pconf_parse_conf()
1112 		ret = stm32_pconf_set_bias(bank, offset, 1);  in stm32_pconf_parse_conf()
1115 		ret = stm32_pconf_set_bias(bank, offset, 2);  in stm32_pconf_parse_conf()
1118 		__stm32_gpio_set(bank, offset, arg);  in stm32_pconf_parse_conf()
1199 	struct stm32_gpio_bank *bank;  in stm32_pconf_dbg_show()  local
1214 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_dbg_show()
1222 	stm32_pmx_get_mode(bank, offset, &mode, &alt);  in stm32_pconf_dbg_show()
1223 	bias = stm32_pconf_get_bias(bank, offset);  in stm32_pconf_dbg_show()
1230 		val = stm32_pconf_get(bank, offset, true);  in stm32_pconf_dbg_show()
1238 		drive = stm32_pconf_get_driving(bank, offset);  in stm32_pconf_dbg_show()
1239 		speed = stm32_pconf_get_speed(bank, offset);  in stm32_pconf_dbg_show()
1240 		val = stm32_pconf_get(bank, offset, false);  in stm32_pconf_dbg_show()
1250 		drive = stm32_pconf_get_driving(bank, offset);  in stm32_pconf_dbg_show()
1251 		speed = stm32_pconf_get_speed(bank, offset);  in stm32_pconf_dbg_show()
1278 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];  in stm32_gpiolib_register_bank()  local
1280 	struct pinctrl_gpio_range *range = &bank->range;  in stm32_gpiolib_register_bank()
1287 	if (!IS_ERR(bank->rstc))  in stm32_gpiolib_register_bank()
1288 		reset_control_deassert(bank->rstc);  in stm32_gpiolib_register_bank()
1293 	bank->base = devm_ioremap_resource(dev, &res);  in stm32_gpiolib_register_bank()
1294 	if (IS_ERR(bank->base))  in stm32_gpiolib_register_bank()
1295 		return PTR_ERR(bank->base);  in stm32_gpiolib_register_bank()
1297 	err = clk_prepare_enable(bank->clk);  in stm32_gpiolib_register_bank()
1303 	bank->gpio_chip = stm32_gpio_template;  in stm32_gpiolib_register_bank()
1305 	fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1309 		bank->gpio_chip.base = args.args[1];  in stm32_gpiolib_register_bank()
1317 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1318 		range->name = bank->gpio_chip.label;  in stm32_gpiolib_register_bank()
1323 		range->gc = &bank->gpio_chip;  in stm32_gpiolib_register_bank()
1328 	if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))  in stm32_gpiolib_register_bank()
1331 	bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1333 	bank->gpio_chip.ngpio = npins;  in stm32_gpiolib_register_bank()
1334 	bank->gpio_chip.fwnode = fwnode;  in stm32_gpiolib_register_bank()
1335 	bank->gpio_chip.parent = dev;  in stm32_gpiolib_register_bank()
1336 	bank->bank_nr = bank_nr;  in stm32_gpiolib_register_bank()
1337 	bank->bank_ioport_nr = bank_ioport_nr;  in stm32_gpiolib_register_bank()
1338 	bank->secure_control = pctl->match_data->secure_control;  in stm32_gpiolib_register_bank()
1339 	spin_lock_init(&bank->lock);  in stm32_gpiolib_register_bank()
1343 		bank->fwnode = fwnode;  in stm32_gpiolib_register_bank()
1345 		bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,  in stm32_gpiolib_register_bank()
1346 							   bank->fwnode, &stm32_gpio_domain_ops,  in stm32_gpiolib_register_bank()
1347 							   bank);  in stm32_gpiolib_register_bank()
1349 		if (!bank->domain) {  in stm32_gpiolib_register_bank()
1355 	err = gpiochip_add_data(&bank->gpio_chip, bank);  in stm32_gpiolib_register_bank()
1361 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1365 	clk_disable_unprepare(bank->clk);  in stm32_gpiolib_register_bank()
1585 		dev_err(dev, "at least one GPIO bank is required\n");  in stm32_pctl_probe()
1595 		struct stm32_gpio_bank *bank = &pctl->banks[i];  in stm32_pctl_probe()  local
1598 		bank->rstc = of_reset_control_get_exclusive(np, NULL);  in stm32_pctl_probe()
1599 		if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {  in stm32_pctl_probe()
1604 		bank->clk = of_clk_get_by_name(np, NULL);  in stm32_pctl_probe()
1605 		if (IS_ERR(bank->clk)) {  in stm32_pctl_probe()
1607 			return dev_err_probe(dev, PTR_ERR(bank->clk),  in stm32_pctl_probe()
1638 	struct stm32_gpio_bank *bank;  in stm32_pinctrl_restore_gpio_regs()  local
1654 	bank = gpiochip_get_data(range->gc);  in stm32_pinctrl_restore_gpio_regs()
1656 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;  in stm32_pinctrl_restore_gpio_regs()
1658 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;  in stm32_pinctrl_restore_gpio_regs()
1661 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);  in stm32_pinctrl_restore_gpio_regs()
1666 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);  in stm32_pinctrl_restore_gpio_regs()
1668 		__stm32_gpio_set(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1671 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);  in stm32_pinctrl_restore_gpio_regs()
1673 	ret = stm32_pconf_set_driving(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1677 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;  in stm32_pinctrl_restore_gpio_regs()
1679 	ret = stm32_pconf_set_speed(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1683 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;  in stm32_pinctrl_restore_gpio_regs()
1685 	ret = stm32_pconf_set_bias(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1690 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);  in stm32_pinctrl_restore_gpio_regs()