1 // SPDX-License-Identifier: GPL-2.0
23 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
26 #include "../pinctrl-utils.h"
30 #define DRIVER_NAME "pinctrl-starfive"
34  * https://github.com/starfive-tech/JH7100_Docs
45  * The following 32-bit registers come in pairs, but only the offset of the
46  * first register is defined. The first controls (interrupts for) GPIO 0-31 and
47  * the second GPIO 32-63.
51  * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
52  * interrupt is level-triggered.
57  * Edge-Trigger Interrupt Type.  If set to 1 the interrupt gets triggered on
58  * both positive and negative edges. If set to 0 the interrupt is triggered by a
64  * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
65  * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
66  * interrupt is triggered on a falling edge (edge-triggered) or low level
67  * (level-triggered).
79  * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
85  * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
90  * Interrupt Status after Masking. A 1 means the configured edge or level was
102  * From the data sheet section 12.2, there are 64 32-bit output data registers
121  * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
141  * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
148  * sfp->gpio.pin_base = PAD_INVALID_GPIO then
157  *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
162  *  |      31       | 30 - 8 |   7 - 0   |
167 	return v & (NR_GPIOS - 1);  in starfive_pinmux_to_gpio()
172 	return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));  in starfive_pinmux_to_dout()
177 	return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));  in starfive_pinmux_to_doen()
200 	return (clamp(i, 14U, 63U) - 14) / 7;  in starfive_drive_strength_from_max_mA()
216 	return pin - sfp->gpios.pin_base;  in starfive_pin_to_gpio()
222 	return sfp->gpios.pin_base + gpio;  in starfive_gpio_to_pin()
461 	reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;  in starfive_pin_dbg_show()
479 	struct device *dev = sfp->gc.parent;  in starfive_dt_node_to_map()
500 			return -EINVAL;  in starfive_dt_node_to_map()
506 			return -EINVAL;  in starfive_dt_node_to_map()
518 		return -ENOMEM;  in starfive_dt_node_to_map()
522 		return -ENOMEM;  in starfive_dt_node_to_map()
526 	mutex_lock(&sfp->mutex);  in starfive_dt_node_to_map()
533 			ret = -ENOMEM;  in starfive_dt_node_to_map()
542 				ret = -ENOMEM;  in starfive_dt_node_to_map()
548 				ret = -ENOMEM;  in starfive_dt_node_to_map()
563 			map[nmaps].data.mux.function = np->name;  in starfive_dt_node_to_map()
569 				ret = -ENOMEM;  in starfive_dt_node_to_map()
584 			ret = -EINVAL;  in starfive_dt_node_to_map()
612 	ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);  in starfive_dt_node_to_map()
614 		dev_err(dev, "error adding function %s: %d\n", np->name, ret);  in starfive_dt_node_to_map()
620 	mutex_unlock(&sfp->mutex);  in starfive_dt_node_to_map()
627 	mutex_unlock(&sfp->mutex);  in starfive_dt_node_to_map()
644 	struct device *dev = sfp->gc.parent;  in starfive_set_mux()
651 		return -EINVAL;  in starfive_set_mux()
653 	pinmux = group->data;  in starfive_set_mux()
654 	for (i = 0; i < group->num_pins; i++) {  in starfive_set_mux()
668 		reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;  in starfive_set_mux()
669 		reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;  in starfive_set_mux()
671 			reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;  in starfive_set_mux()
675 		raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_set_mux()
680 		raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_set_mux()
697 	void __iomem *reg = sfp->padctl + 4 * (pin / 2);  in starfive_padctl_get()
707 	void __iomem *reg = sfp->padctl + 4 * (pin / 2);  in starfive_padctl_rmw()
713 	dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);  in starfive_padctl_rmw()
715 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_padctl_rmw()
718 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_padctl_rmw()
724 	{ "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
729 	PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
781 		return -ENOTSUPP;  in starfive_pinconf_get()
785 	return enabled ? 0 : -EINVAL;  in starfive_pinconf_get()
795 		return -EINVAL;  in starfive_pinconf_group_get()
797 	return starfive_pinconf_get(pctldev, group->pins[0], config);  in starfive_pinconf_group_get()
812 		return -EINVAL;  in starfive_pinconf_group_set()
827 				return -ENOTSUPP;  in starfive_pinconf_group_set()
833 				return -ENOTSUPP;  in starfive_pinconf_group_set()
872 			return -ENOTSUPP;  in starfive_pinconf_group_set()
876 	for (i = 0; i < group->num_pins; i++)  in starfive_pinconf_group_set()
877 		starfive_padctl_rmw(sfp, group->pins[i], mask, value);  in starfive_pinconf_group_set()
918 	return pinctrl_gpio_request(gc->base + gpio);  in starfive_gpio_request()
923 	pinctrl_gpio_free(gc->base + gpio);  in starfive_gpio_free()
929 	void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;  in starfive_gpio_get_direction()
941 	void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;  in starfive_gpio_direction_input()
949 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_gpio_direction_input()
951 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_gpio_direction_input()
959 	void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;  in starfive_gpio_direction_output()
960 	void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;  in starfive_gpio_direction_output()
963 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_gpio_direction_output()
966 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_gpio_direction_output()
979 	void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);  in starfive_gpio_get()
988 	void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;  in starfive_gpio_set()
991 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_gpio_set()
993 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_gpio_set()
1011 			return -ENOTSUPP;  in starfive_gpio_set_config()
1017 			return -ENOTSUPP;  in starfive_gpio_set_config()
1032 		return -ENOTSUPP;  in starfive_gpio_set_config()
1043 	sfp->gpios.name = sfp->gc.label;  in starfive_gpio_add_pin_ranges()
1044 	sfp->gpios.base = sfp->gc.base;  in starfive_gpio_add_pin_ranges()
1046 	 * sfp->gpios.pin_base depends on the chosen signal group  in starfive_gpio_add_pin_ranges()
1049 	sfp->gpios.npins = NR_GPIOS;  in starfive_gpio_add_pin_ranges()
1050 	sfp->gpios.gc = &sfp->gc;  in starfive_gpio_add_pin_ranges()
1051 	pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);  in starfive_gpio_add_pin_ranges()
1059 	void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);  in starfive_irq_ack()
1063 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_ack()
1065 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_ack()
1072 	void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);  in starfive_irq_mask()
1077 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_mask()
1080 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_mask()
1082 	gpiochip_disable_irq(&sfp->gc, d->hwirq);  in starfive_irq_mask()
1089 	void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);  in starfive_irq_mask_ack()
1090 	void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);  in starfive_irq_mask_ack()
1095 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_mask_ack()
1099 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_mask_ack()
1106 	void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);  in starfive_irq_unmask()
1111 	gpiochip_enable_irq(&sfp->gc, d->hwirq);  in starfive_irq_unmask()
1113 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_unmask()
1116 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_unmask()
1123 	void __iomem *base = sfp->base + 4 * (gpio / 32);  in starfive_irq_set_type()
1130 		irq_type  = mask; /* 1: edge triggered */  in starfive_irq_set_type()
1135 		irq_type  = mask; /* 1: edge triggered */  in starfive_irq_set_type()
1140 		irq_type  = mask; /* 1: edge triggered */  in starfive_irq_set_type()
1145 		irq_type  = 0;    /* 0: level triggered */  in starfive_irq_set_type()
1147 		polarity  = mask; /* 1: high level */  in starfive_irq_set_type()
1150 		irq_type  = 0;    /* 0: level triggered */  in starfive_irq_set_type()
1152 		polarity  = 0;    /* 0: low level */  in starfive_irq_set_type()
1155 		return -EINVAL;  in starfive_irq_set_type()
1163 	raw_spin_lock_irqsave(&sfp->lock, flags);  in starfive_irq_set_type()
1170 	raw_spin_unlock_irqrestore(&sfp->lock, flags);  in starfive_irq_set_type()
1194 	mis = readl_relaxed(sfp->base + GPIOMIS + 0);  in starfive_gpio_irq_handler()
1196 		generic_handle_domain_irq(sfp->gc.irq.domain, pin);  in starfive_gpio_irq_handler()
1198 	mis = readl_relaxed(sfp->base + GPIOMIS + 4);  in starfive_gpio_irq_handler()
1200 		generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);  in starfive_gpio_irq_handler()
1210 	writel(0, sfp->base + GPIOIE + 0);  in starfive_gpio_init_hw()
1211 	writel(0, sfp->base + GPIOIE + 4);  in starfive_gpio_init_hw()
1213 	writel(~0U, sfp->base + GPIOIC + 0);  in starfive_gpio_init_hw()
1214 	writel(~0U, sfp->base + GPIOIC + 4);  in starfive_gpio_init_hw()
1216 	writel(1, sfp->base + GPIOEN);  in starfive_gpio_init_hw()
1227 	struct device *dev = &pdev->dev;  in starfive_probe()
1236 		return -ENOMEM;  in starfive_probe()
1238 	sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");  in starfive_probe()
1239 	if (IS_ERR(sfp->base))  in starfive_probe()
1240 		return PTR_ERR(sfp->base);  in starfive_probe()
1242 	sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");  in starfive_probe()
1243 	if (IS_ERR(sfp->padctl))  in starfive_probe()
1244 		return PTR_ERR(sfp->padctl);  in starfive_probe()
1272 	sfp->gc.parent = dev;  in starfive_probe()
1273 	raw_spin_lock_init(&sfp->lock);  in starfive_probe()
1274 	mutex_init(&sfp->mutex);  in starfive_probe()
1276 	ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);  in starfive_probe()
1280 	if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {  in starfive_probe()
1282 			return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);  in starfive_probe()
1283 		writel(value, sfp->padctl + IO_PADSHARE_SEL);  in starfive_probe()
1286 	value = readl(sfp->padctl + IO_PADSHARE_SEL);  in starfive_probe()
1289 		sfp->gpios.pin_base = PAD_INVALID_GPIO;  in starfive_probe()
1292 		sfp->gpios.pin_base = PAD_GPIO(0);  in starfive_probe()
1295 		sfp->gpios.pin_base = PAD_FUNC_SHARE(72);  in starfive_probe()
1298 		sfp->gpios.pin_base = PAD_FUNC_SHARE(70);  in starfive_probe()
1301 		sfp->gpios.pin_base = PAD_FUNC_SHARE(0);  in starfive_probe()
1304 		return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);  in starfive_probe()
1307 	sfp->gc.label = dev_name(dev);  in starfive_probe()
1308 	sfp->gc.owner = THIS_MODULE;  in starfive_probe()
1309 	sfp->gc.request = starfive_gpio_request;  in starfive_probe()
1310 	sfp->gc.free = starfive_gpio_free;  in starfive_probe()
1311 	sfp->gc.get_direction = starfive_gpio_get_direction;  in starfive_probe()
1312 	sfp->gc.direction_input = starfive_gpio_direction_input;  in starfive_probe()
1313 	sfp->gc.direction_output = starfive_gpio_direction_output;  in starfive_probe()
1314 	sfp->gc.get = starfive_gpio_get;  in starfive_probe()
1315 	sfp->gc.set = starfive_gpio_set;  in starfive_probe()
1316 	sfp->gc.set_config = starfive_gpio_set_config;  in starfive_probe()
1317 	sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;  in starfive_probe()
1318 	sfp->gc.base = -1;  in starfive_probe()
1319 	sfp->gc.ngpio = NR_GPIOS;  in starfive_probe()
1321 	gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);  in starfive_probe()
1322 	sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;  in starfive_probe()
1323 	sfp->gc.irq.num_parents = 1;  in starfive_probe()
1324 	sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,  in starfive_probe()
1325 					   sizeof(*sfp->gc.irq.parents), GFP_KERNEL);  in starfive_probe()
1326 	if (!sfp->gc.irq.parents)  in starfive_probe()
1327 		return -ENOMEM;  in starfive_probe()
1328 	sfp->gc.irq.default_type = IRQ_TYPE_NONE;  in starfive_probe()
1329 	sfp->gc.irq.handler = handle_bad_irq;  in starfive_probe()
1330 	sfp->gc.irq.init_hw = starfive_gpio_init_hw;  in starfive_probe()
1335 	sfp->gc.irq.parents[0] = ret;  in starfive_probe()
1337 	ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);  in starfive_probe()
1341 	irq_domain_set_pm_device(sfp->gc.irq.domain, dev);  in starfive_probe()
1344 	return pinctrl_enable(sfp->pctl);  in starfive_probe()
1348 	{ .compatible = "starfive,jh7100-pinctrl" },