8 #define DRV_NAME "sh-pfc"
37 	struct sh_pfc *pfc;  member
51 	return pmx->pfc->info->nr_groups;  in sh_pfc_get_groups_count()
59 	return pmx->pfc->info->groups[selector].name;  in sh_pfc_get_group_name()
67 	*pins = pmx->pfc->info->groups[selector].pins;  in sh_pfc_get_group_pins()
68 	*num_pins = pmx->pfc->info->groups[selector].nr_pins;  in sh_pfc_get_group_pins()
107 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_subnode_to_map()
262 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_node_to_map()
317 	return pmx->pfc->info->nr_functions;  in sh_pfc_get_functions_count()
325 	return pmx->pfc->info->functions[selector].name;  in sh_pfc_get_function_name()
335 	*groups = pmx->pfc->info->functions[selector].groups;  in sh_pfc_get_function_groups()
336 	*num_groups = pmx->pfc->info->functions[selector].nr_groups;  in sh_pfc_get_function_groups()
345 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_func_set_mux()  local
346 	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];  in sh_pfc_func_set_mux()
353 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_func_set_mux()
356 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
368 		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);  in sh_pfc_func_set_mux()
375 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
382 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_func_set_mux()
391 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_request_enable()  local
392 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_request_enable()
397 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
399 	if (!pfc->gpio && !cfg->mux_mark) {  in sh_pfc_gpio_request_enable()
403 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_request_enable()
405 		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);  in sh_pfc_gpio_request_enable()
415 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
425 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_disable_free()  local
426 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_disable_free()
430 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
434 		sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);  in sh_pfc_gpio_disable_free()
435 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
444 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_set_direction()  local
446 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_set_direction()
447 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_set_direction()
461 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
462 	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);  in sh_pfc_gpio_set_direction()
463 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
480 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,  in sh_pfc_pinconf_find_drive_strength_reg()  argument
487 	for (reg = pfc->info->drive_regs; reg->reg; ++reg) {  in sh_pfc_pinconf_find_drive_strength_reg()
503 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_get_drive_strength()  argument
511 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_get_drive_strength()
515 	val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0);  in sh_pfc_pinconf_get_drive_strength()
523 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_set_drive_strength()  argument
533 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_set_drive_strength()
547 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
549 	val = sh_pfc_read(pfc, reg);  in sh_pfc_pinconf_set_drive_strength()
553 	sh_pfc_write(pfc, reg, val);  in sh_pfc_pinconf_set_drive_strength()
555 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
561 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,  in sh_pfc_pinconf_validate()  argument
564 	int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_validate()
565 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_validate()
592 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_get()  local
597 	if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_get()
606 		if (!pfc->info->ops || !pfc->info->ops->get_bias)  in sh_pfc_pinconf_get()
609 		spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get()
610 		bias = pfc->info->ops->get_bias(pfc, _pin);  in sh_pfc_pinconf_get()
611 		spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get()
623 		ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);  in sh_pfc_pinconf_get()
632 		int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_get()
633 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_get()
638 		if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_get()
641 		bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);  in sh_pfc_pinconf_get()
645 		val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_get()
666 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_set()  local
674 		if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_set()
681 			if (!pfc->info->ops || !pfc->info->ops->set_bias)  in sh_pfc_pinconf_set()
684 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
685 			pfc->info->ops->set_bias(pfc, _pin, param);  in sh_pfc_pinconf_set()
686 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
695 			ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);  in sh_pfc_pinconf_set()
704 			int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_set()
705 			const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_set()
710 			if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_set()
713 			bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);  in sh_pfc_pinconf_set()
723 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
724 			val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_set()
729 			sh_pfc_write(pfc, pocctrl, val);  in sh_pfc_pinconf_set()
730 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
752 	pins = pmx->pfc->info->groups[group].pins;  in sh_pfc_pinconf_group_set()
753 	num_pins = pmx->pfc->info->groups[group].nr_pins;  in sh_pfc_pinconf_group_set()
772 /* PFC ranges -> pinctrl pin descs */
773 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)  in sh_pfc_map_pins()  argument
778 	pmx->pins = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
779 				 pfc->info->nr_pins, sizeof(*pmx->pins),  in sh_pfc_map_pins()
784 	pmx->configs = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
785 				    pfc->info->nr_pins, sizeof(*pmx->configs),  in sh_pfc_map_pins()
790 	for (i = 0; i < pfc->info->nr_pins; ++i) {  in sh_pfc_map_pins()
791 		const struct sh_pfc_pin *info = &pfc->info->pins[i];  in sh_pfc_map_pins()
802 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)  in sh_pfc_register_pinctrl()  argument
807 	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);  in sh_pfc_register_pinctrl()
811 	pmx->pfc = pfc;  in sh_pfc_register_pinctrl()
813 	ret = sh_pfc_map_pins(pfc, pmx);  in sh_pfc_register_pinctrl()
823 	pmx->pctl_desc.npins = pfc->info->nr_pins;  in sh_pfc_register_pinctrl()
825 	ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,  in sh_pfc_register_pinctrl()
828 		dev_err(pfc->dev, "could not register: %i\n", ret);  in sh_pfc_register_pinctrl()
856 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)  in rcar_pinmux_get_bias()  argument
861 	reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);  in rcar_pinmux_get_bias()
866 		if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))  in rcar_pinmux_get_bias()
868 		else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))  in rcar_pinmux_get_bias()
873 		if (sh_pfc_read(pfc, reg->pud) & BIT(bit))  in rcar_pinmux_get_bias()
880 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,  in rcar_pinmux_set_bias()  argument
887 	reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);  in rcar_pinmux_set_bias()
892 		enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);  in rcar_pinmux_set_bias()
897 				updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);  in rcar_pinmux_set_bias()
901 				sh_pfc_write(pfc, reg->pud, updown);  in rcar_pinmux_set_bias()
904 		sh_pfc_write(pfc, reg->puen, enable);  in rcar_pinmux_set_bias()
906 		enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);  in rcar_pinmux_set_bias()
910 		sh_pfc_write(pfc, reg->pud, enable);  in rcar_pinmux_set_bias()
919 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)  in rmobile_pinmux_get_bias()  argument
921 	void __iomem *reg = pfc->windows->virt +  in rmobile_pinmux_get_bias()
922 			    pfc->info->ops->pin_to_portcr(pin);  in rmobile_pinmux_get_bias()
936 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,  in rmobile_pinmux_set_bias()  argument
939 	void __iomem *reg = pfc->windows->virt +  in rmobile_pinmux_set_bias()
940 			    pfc->info->ops->pin_to_portcr(pin);  in rmobile_pinmux_set_bias()