Lines Matching +full:rzv2m +full:- +full:pinctrl
1 // SPDX-License-Identifier: GPL-2.0
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
24 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
30 #define DRV_NAME "pinctrl-rzv2m"
144 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
145 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
148 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; in rzv2m_pinctrl_set_pfc_mode()
152 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0); in rzv2m_pinctrl_set_pfc_mode()
153 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0); in rzv2m_pinctrl_set_pfc_mode()
168 return -EINVAL; in rzv2m_pinctrl_set_mux()
171 return -EINVAL; in rzv2m_pinctrl_set_mux()
173 psel_val = func->data; in rzv2m_pinctrl_set_mux()
174 pins = group->pins; in rzv2m_pinctrl_set_mux()
176 for (i = 0; i < group->num_pins; i++) { in rzv2m_pinctrl_set_mux()
177 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", in rzv2m_pinctrl_set_mux()
198 return -ENOMEM; in rzv2m_map_add_config()
200 map->type = type; in rzv2m_map_add_config()
201 map->data.configs.group_or_pin = group_or_pin; in rzv2m_map_add_config()
202 map->data.configs.configs = cfgs; in rzv2m_map_add_config()
203 map->data.configs.num_configs = num_configs; in rzv2m_map_add_config()
231 num_pinmux = pinmux->length / sizeof(u32); in rzv2m_dt_subnode_to_map()
234 if (ret == -EINVAL) { in rzv2m_dt_subnode_to_map()
237 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzv2m_dt_subnode_to_map()
247 dev_err(pctrl->dev, in rzv2m_dt_subnode_to_map()
249 return -EINVAL; in rzv2m_dt_subnode_to_map()
257 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzv2m_dt_subnode_to_map()
258 ret = -ENODEV; in rzv2m_dt_subnode_to_map()
270 ret = -ENOMEM; in rzv2m_dt_subnode_to_map()
290 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzv2m_dt_subnode_to_map()
291 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzv2m_dt_subnode_to_map()
293 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzv2m_dt_subnode_to_map()
295 ret = -ENOMEM; in rzv2m_dt_subnode_to_map()
311 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); in rzv2m_dt_subnode_to_map()
321 pin_fn[0] = np->name; in rzv2m_dt_subnode_to_map()
322 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, in rzv2m_dt_subnode_to_map()
330 maps[idx].data.mux.group = np->name; in rzv2m_dt_subnode_to_map()
331 maps[idx].data.mux.function = np->name; in rzv2m_dt_subnode_to_map()
334 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzv2m_dt_subnode_to_map()
396 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzv2m_dt_node_to_map()
397 ret = -EINVAL; in rzv2m_dt_node_to_map()
413 if (bit >= pincount || port >= pctrl->data->n_port_pins) in rzv2m_validate_gpio_pin()
414 return -EINVAL; in rzv2m_validate_gpio_pin()
416 data = pctrl->data->port_pin_configs[port]; in rzv2m_validate_gpio_pin()
418 return -EINVAL; in rzv2m_validate_gpio_pin()
426 void __iomem *addr = pctrl->base + offset; in rzv2m_rmw_pin_config()
430 spin_lock_irqsave(&pctrl->lock, flags); in rzv2m_rmw_pin_config()
433 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2m_rmw_pin_config()
442 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzv2m_pinctrl_pinconf_get()
443 unsigned int *pin_data = pin->drv_data; in rzv2m_pinctrl_pinconf_get()
451 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
463 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
473 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
475 /* PUPD uses 2-bits per pin */ in rzv2m_pinctrl_pinconf_get()
478 switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) { in rzv2m_pinctrl_pinconf_get()
490 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
496 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
498 /* DRV uses 2-bits per pin */ in rzv2m_pinctrl_pinconf_get()
501 val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK; in rzv2m_pinctrl_pinconf_get()
518 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
525 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
527 arg = readl(pctrl->base + SR(port)) & BIT(bit); in rzv2m_pinctrl_pinconf_get()
531 return -ENOTSUPP; in rzv2m_pinctrl_pinconf_get()
545 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzv2m_pinctrl_pinconf_set()
546 unsigned int *pin_data = pin->drv_data; in rzv2m_pinctrl_pinconf_set()
555 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
567 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
577 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
579 /* PUPD uses 2-bits per pin */ in rzv2m_pinctrl_pinconf_set()
602 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
619 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
627 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
629 /* DRV uses 2-bits per pin */ in rzv2m_pinctrl_pinconf_set()
640 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
642 rzv2m_writel_we(pctrl->base + SR(port), bit, !arg); in rzv2m_pinctrl_pinconf_set()
647 return -EOPNOTSUPP; in rzv2m_pinctrl_pinconf_set()
696 return -EOPNOTSUPP; in rzv2m_pinctrl_pinconf_group_get()
736 ret = pinctrl_gpio_request(chip->base + offset); in rzv2m_gpio_request()
748 rzv2m_writel_we(pctrl->base + OE(port), bit, output); in rzv2m_gpio_set_direction()
749 rzv2m_writel_we(pctrl->base + IE(port), bit, !output); in rzv2m_gpio_set_direction()
758 if (!(readl(pctrl->base + IE(port)) & BIT(bit))) in rzv2m_gpio_get_direction()
783 rzv2m_writel_we(pctrl->base + DO(port), bit, !!value); in rzv2m_gpio_set()
807 return !!(readl(pctrl->base + DI(port)) & BIT(bit)); in rzv2m_gpio_get()
809 return !!(readl(pctrl->base + DO(port)) & BIT(bit)); in rzv2m_gpio_get()
814 pinctrl_gpio_free(chip->base + offset); in rzv2m_gpio_free()
914 struct device_node *np = pctrl->dev->of_node; in rzv2m_gpio_register()
915 struct gpio_chip *chip = &pctrl->gpio_chip; in rzv2m_gpio_register()
916 const char *name = dev_name(pctrl->dev); in rzv2m_gpio_register()
920 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); in rzv2m_gpio_register()
922 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); in rzv2m_gpio_register()
927 of_args.args[2] != pctrl->data->n_port_pins) { in rzv2m_gpio_register()
928 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); in rzv2m_gpio_register()
929 return -EINVAL; in rzv2m_gpio_register()
932 chip->names = pctrl->data->port_pins; in rzv2m_gpio_register()
933 chip->request = rzv2m_gpio_request; in rzv2m_gpio_register()
934 chip->free = rzv2m_gpio_free; in rzv2m_gpio_register()
935 chip->get_direction = rzv2m_gpio_get_direction; in rzv2m_gpio_register()
936 chip->direction_input = rzv2m_gpio_direction_input; in rzv2m_gpio_register()
937 chip->direction_output = rzv2m_gpio_direction_output; in rzv2m_gpio_register()
938 chip->get = rzv2m_gpio_get; in rzv2m_gpio_register()
939 chip->set = rzv2m_gpio_set; in rzv2m_gpio_register()
940 chip->label = name; in rzv2m_gpio_register()
941 chip->parent = pctrl->dev; in rzv2m_gpio_register()
942 chip->owner = THIS_MODULE; in rzv2m_gpio_register()
943 chip->base = -1; in rzv2m_gpio_register()
944 chip->ngpio = of_args.args[2]; in rzv2m_gpio_register()
946 pctrl->gpio_range.id = 0; in rzv2m_gpio_register()
947 pctrl->gpio_range.pin_base = 0; in rzv2m_gpio_register()
948 pctrl->gpio_range.base = 0; in rzv2m_gpio_register()
949 pctrl->gpio_range.npins = chip->ngpio; in rzv2m_gpio_register()
950 pctrl->gpio_range.name = chip->label; in rzv2m_gpio_register()
951 pctrl->gpio_range.gc = chip; in rzv2m_gpio_register()
952 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzv2m_gpio_register()
954 dev_err(pctrl->dev, "failed to add GPIO controller\n"); in rzv2m_gpio_register()
958 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzv2m_gpio_register()
970 pctrl->desc.name = DRV_NAME; in rzv2m_pinctrl_register()
971 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzv2m_pinctrl_register()
972 pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops; in rzv2m_pinctrl_register()
973 pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops; in rzv2m_pinctrl_register()
974 pctrl->desc.confops = &rzv2m_pinctrl_confops; in rzv2m_pinctrl_register()
975 pctrl->desc.owner = THIS_MODULE; in rzv2m_pinctrl_register()
977 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzv2m_pinctrl_register()
979 return -ENOMEM; in rzv2m_pinctrl_register()
981 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzv2m_pinctrl_register()
984 return -ENOMEM; in rzv2m_pinctrl_register()
986 pctrl->pins = pins; in rzv2m_pinctrl_register()
987 pctrl->desc.pins = pins; in rzv2m_pinctrl_register()
989 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzv2m_pinctrl_register()
991 pins[i].name = pctrl->data->port_pins[i]; in rzv2m_pinctrl_register()
994 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzv2m_pinctrl_register()
998 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzv2m_pinctrl_register()
999 unsigned int index = pctrl->data->n_port_pins + i; in rzv2m_pinctrl_register()
1002 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzv2m_pinctrl_register()
1003 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzv2m_pinctrl_register()
1007 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzv2m_pinctrl_register()
1008 &pctrl->pctl); in rzv2m_pinctrl_register()
1010 dev_err(pctrl->dev, "pinctrl registration failed\n"); in rzv2m_pinctrl_register()
1014 ret = pinctrl_enable(pctrl->pctl); in rzv2m_pinctrl_register()
1016 dev_err(pctrl->dev, "pinctrl enable failed\n"); in rzv2m_pinctrl_register()
1022 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); in rzv2m_pinctrl_register()
1039 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzv2m_pinctrl_probe()
1041 return -ENOMEM; in rzv2m_pinctrl_probe()
1043 pctrl->dev = &pdev->dev; in rzv2m_pinctrl_probe()
1045 pctrl->data = of_device_get_match_data(&pdev->dev); in rzv2m_pinctrl_probe()
1046 if (!pctrl->data) in rzv2m_pinctrl_probe()
1047 return -EINVAL; in rzv2m_pinctrl_probe()
1049 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzv2m_pinctrl_probe()
1050 if (IS_ERR(pctrl->base)) in rzv2m_pinctrl_probe()
1051 return PTR_ERR(pctrl->base); in rzv2m_pinctrl_probe()
1053 pctrl->clk = devm_clk_get(pctrl->dev, NULL); in rzv2m_pinctrl_probe()
1054 if (IS_ERR(pctrl->clk)) { in rzv2m_pinctrl_probe()
1055 ret = PTR_ERR(pctrl->clk); in rzv2m_pinctrl_probe()
1056 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); in rzv2m_pinctrl_probe()
1060 spin_lock_init(&pctrl->lock); in rzv2m_pinctrl_probe()
1064 ret = clk_prepare_enable(pctrl->clk); in rzv2m_pinctrl_probe()
1066 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); in rzv2m_pinctrl_probe()
1070 ret = devm_add_action_or_reset(&pdev->dev, rzv2m_pinctrl_clk_disable, in rzv2m_pinctrl_probe()
1071 pctrl->clk); in rzv2m_pinctrl_probe()
1073 dev_err(pctrl->dev, in rzv2m_pinctrl_probe()
1083 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzv2m_pinctrl_probe()
1097 .compatible = "renesas,r9a09g011-pinctrl",