1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/pinctrl/pinconf-generic.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
22 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
28 #define DRV_NAME	"pinctrl-rzg2l"
163 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_pinctrl_set_pfc_mode()
165 	/* Set pin to 'Non-use (Hi-Z input protection)'  */  in rzg2l_pinctrl_set_pfc_mode()
166 	reg = readw(pctrl->base + PM(port));  in rzg2l_pinctrl_set_pfc_mode()
168 	writew(reg, pctrl->base + PM(port));  in rzg2l_pinctrl_set_pfc_mode()
171 	reg = readb(pctrl->base + PMC(port));  in rzg2l_pinctrl_set_pfc_mode()
172 	writeb(reg & ~BIT(pin), pctrl->base + PMC(port));  in rzg2l_pinctrl_set_pfc_mode()
175 	writel(0x0, pctrl->base + PWPR);        /* B0WI=0, PFCWE=0 */  in rzg2l_pinctrl_set_pfc_mode()
176 	writel(PWPR_PFCWE, pctrl->base + PWPR);  /* B0WI=0, PFCWE=1 */  in rzg2l_pinctrl_set_pfc_mode()
179 	reg = readl(pctrl->base + PFC(port));  in rzg2l_pinctrl_set_pfc_mode()
181 	writel(reg | (func << (pin * 4)), pctrl->base + PFC(port));  in rzg2l_pinctrl_set_pfc_mode()
183 	/* Set the PWPR register to be write-protected */  in rzg2l_pinctrl_set_pfc_mode()
184 	writel(0x0, pctrl->base + PWPR);        /* B0WI=0, PFCWE=0 */  in rzg2l_pinctrl_set_pfc_mode()
185 	writel(PWPR_B0WI, pctrl->base + PWPR);  /* B0WI=1, PFCWE=0 */  in rzg2l_pinctrl_set_pfc_mode()
188 	reg = readb(pctrl->base + PMC(port));  in rzg2l_pinctrl_set_pfc_mode()
189 	writeb(reg | BIT(pin), pctrl->base + PMC(port));  in rzg2l_pinctrl_set_pfc_mode()
191 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_pinctrl_set_pfc_mode()
206 		return -EINVAL;  in rzg2l_pinctrl_set_mux()
209 		return -EINVAL;  in rzg2l_pinctrl_set_mux()
211 	psel_val = func->data;  in rzg2l_pinctrl_set_mux()
212 	pins = group->pins;  in rzg2l_pinctrl_set_mux()
214 	for (i = 0; i < group->num_pins; i++) {  in rzg2l_pinctrl_set_mux()
215 		dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",  in rzg2l_pinctrl_set_mux()
236 		return -ENOMEM;  in rzg2l_map_add_config()
238 	map->type = type;  in rzg2l_map_add_config()
239 	map->data.configs.group_or_pin = group_or_pin;  in rzg2l_map_add_config()
240 	map->data.configs.configs = cfgs;  in rzg2l_map_add_config()
241 	map->data.configs.num_configs = num_configs;  in rzg2l_map_add_config()
269 		num_pinmux = pinmux->length / sizeof(u32);  in rzg2l_dt_subnode_to_map()
272 	if (ret == -EINVAL) {  in rzg2l_dt_subnode_to_map()
275 		dev_err(pctrl->dev, "Invalid pins list in DT\n");  in rzg2l_dt_subnode_to_map()
285 		dev_err(pctrl->dev,  in rzg2l_dt_subnode_to_map()
287 		return -EINVAL;  in rzg2l_dt_subnode_to_map()
295 		dev_err(pctrl->dev, "DT node must contain a config\n");  in rzg2l_dt_subnode_to_map()
296 		ret = -ENODEV;  in rzg2l_dt_subnode_to_map()
308 		ret = -ENOMEM;  in rzg2l_dt_subnode_to_map()
328 	pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);  in rzg2l_dt_subnode_to_map()
329 	psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),  in rzg2l_dt_subnode_to_map()
331 	pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);  in rzg2l_dt_subnode_to_map()
333 		ret = -ENOMEM;  in rzg2l_dt_subnode_to_map()
349 	gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);  in rzg2l_dt_subnode_to_map()
359 	pin_fn[0] = np->name;  in rzg2l_dt_subnode_to_map()
360 	fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,  in rzg2l_dt_subnode_to_map()
368 	maps[idx].data.mux.group = np->name;  in rzg2l_dt_subnode_to_map()
369 	maps[idx].data.mux.function = np->name;  in rzg2l_dt_subnode_to_map()
372 	dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);  in rzg2l_dt_subnode_to_map()
434 	dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);  in rzg2l_dt_node_to_map()
435 	ret = -EINVAL;  in rzg2l_dt_node_to_map()
451 	if (bit >= pincount || port >= pctrl->data->n_port_pins)  in rzg2l_validate_gpio_pin()
452 		return -EINVAL;  in rzg2l_validate_gpio_pin()
454 	data = pctrl->data->port_pin_configs[port];  in rzg2l_validate_gpio_pin()
456 		return -EINVAL;  in rzg2l_validate_gpio_pin()
464 	void __iomem *addr = pctrl->base + offset;  in rzg2l_read_pin_config()
466 	/* handle _L/_H for 32-bit register read/write */  in rzg2l_read_pin_config()
468 		bit -= 4;  in rzg2l_read_pin_config()
478 	void __iomem *addr = pctrl->base + offset;  in rzg2l_rmw_pin_config()
482 	/* handle _L/_H for 32-bit register read/write */  in rzg2l_rmw_pin_config()
484 		bit -= 4;  in rzg2l_rmw_pin_config()
488 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_rmw_pin_config()
491 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_rmw_pin_config()
500 	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];  in rzg2l_pinctrl_pinconf_get()
501 	unsigned int *pin_data = pin->drv_data;  in rzg2l_pinctrl_pinconf_get()
510 		return -EINVAL;  in rzg2l_pinctrl_pinconf_get()
522 			return -EINVAL;  in rzg2l_pinctrl_pinconf_get()
528 			return -EINVAL;  in rzg2l_pinctrl_pinconf_get()
531 			return -EINVAL;  in rzg2l_pinctrl_pinconf_get()
544 			return -EINVAL;  in rzg2l_pinctrl_pinconf_get()
546 		spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_pinctrl_pinconf_get()
547 		addr = pctrl->base + pwr_reg;  in rzg2l_pinctrl_pinconf_get()
549 		spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_pinctrl_pinconf_get()
557 			return -EINVAL;  in rzg2l_pinctrl_pinconf_get()
568 			return -EINVAL;  in rzg2l_pinctrl_pinconf_get()
576 		return -ENOTSUPP;  in rzg2l_pinctrl_pinconf_get()
590 	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];  in rzg2l_pinctrl_pinconf_set()
591 	unsigned int *pin_data = pin->drv_data;  in rzg2l_pinctrl_pinconf_set()
601 		return -EINVAL;  in rzg2l_pinctrl_pinconf_set()
613 			return -EINVAL;  in rzg2l_pinctrl_pinconf_set()
624 				return -EINVAL;  in rzg2l_pinctrl_pinconf_set()
635 				return -EINVAL;  in rzg2l_pinctrl_pinconf_set()
644 				return -EINVAL;  in rzg2l_pinctrl_pinconf_set()
646 			addr = pctrl->base + pwr_reg;  in rzg2l_pinctrl_pinconf_set()
647 			spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_pinctrl_pinconf_set()
649 			spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_pinctrl_pinconf_set()
658 				return -EINVAL;  in rzg2l_pinctrl_pinconf_set()
665 				return -EINVAL;  in rzg2l_pinctrl_pinconf_set()
676 				return -EINVAL;  in rzg2l_pinctrl_pinconf_set()
683 				return -EINVAL;  in rzg2l_pinctrl_pinconf_set()
690 			return -EOPNOTSUPP;  in rzg2l_pinctrl_pinconf_set()
739 			return -EOPNOTSUPP;  in rzg2l_pinctrl_pinconf_group_get()
781 	ret = pinctrl_gpio_request(chip->base + offset);  in rzg2l_gpio_request()
785 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_request()
788 	reg8 = readb(pctrl->base + PMC(port));  in rzg2l_gpio_request()
790 	writeb(reg8, pctrl->base + PMC(port));  in rzg2l_gpio_request()
792 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_request()
803 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_set_direction()
805 	reg16 = readw(pctrl->base + PM(port));  in rzg2l_gpio_set_direction()
809 	writew(reg16, pctrl->base + PM(port));  in rzg2l_gpio_set_direction()
811 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_set_direction()
820 	if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) {  in rzg2l_gpio_get_direction()
823 		reg16 = readw(pctrl->base + PM(port));  in rzg2l_gpio_get_direction()
853 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_set()
855 	reg8 = readb(pctrl->base + P(port));  in rzg2l_gpio_set()
858 		writeb(reg8 | BIT(bit), pctrl->base + P(port));  in rzg2l_gpio_set()
860 		writeb(reg8 & ~BIT(bit), pctrl->base + P(port));  in rzg2l_gpio_set()
862 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_set()
885 	reg16 = readw(pctrl->base + PM(port));  in rzg2l_gpio_get()
889 		return !!(readb(pctrl->base + PIN(port)) & BIT(bit));  in rzg2l_gpio_get()
891 		return !!(readb(pctrl->base + P(port)) & BIT(bit));  in rzg2l_gpio_get()
893 		return -EINVAL;  in rzg2l_gpio_get()
900 	pinctrl_gpio_free(chip->base + offset);  in rzg2l_gpio_free()
902 	virq = irq_find_mapping(chip->irq.domain, offset);  in rzg2l_gpio_free()
1136 		return -EINVAL;  in rzg2l_gpio_get_gpioint()
1158 	addr = pctrl->base + ISEL(port);  in rzg2l_gpio_irq_disable()
1160 		bit -= 4;  in rzg2l_gpio_irq_disable()
1164 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_irq_disable()
1166 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_irq_disable()
1187 	addr = pctrl->base + ISEL(port);  in rzg2l_gpio_irq_enable()
1189 		bit -= 4;  in rzg2l_gpio_irq_enable()
1193 	spin_lock_irqsave(&pctrl->lock, flags);  in rzg2l_gpio_irq_enable()
1195 	spin_unlock_irqrestore(&pctrl->lock, flags);  in rzg2l_gpio_irq_enable()
1214 	seq_printf(p, dev_name(gc->parent));  in rzg2l_gpio_irq_print_chip()
1218 	.name = "rzg2l-gpio",
1244 	spin_lock_irqsave(&pctrl->bitmap_lock, flags);  in rzg2l_gpio_child_to_parent_hwirq()
1245 	irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1));  in rzg2l_gpio_child_to_parent_hwirq()
1246 	spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);  in rzg2l_gpio_child_to_parent_hwirq()
1248 		return -ENOSPC;  in rzg2l_gpio_child_to_parent_hwirq()
1249 	pctrl->hwirq[irq] = child;  in rzg2l_gpio_child_to_parent_hwirq()
1263 	struct irq_fwspec *fwspec = &gfwspec->fwspec;  in rzg2l_gpio_populate_parent_fwspec()
1265 	fwspec->fwnode = chip->irq.parent_domain->fwnode;  in rzg2l_gpio_populate_parent_fwspec()
1266 	fwspec->param_count = 2;  in rzg2l_gpio_populate_parent_fwspec()
1267 	fwspec->param[0] = parent_hwirq;  in rzg2l_gpio_populate_parent_fwspec()
1268 	fwspec->param[1] = parent_type;  in rzg2l_gpio_populate_parent_fwspec()
1287 			if (pctrl->hwirq[i] == hwirq) {  in rzg2l_gpio_irq_domain_free()
1288 				spin_lock_irqsave(&pctrl->bitmap_lock, flags);  in rzg2l_gpio_irq_domain_free()
1289 				bitmap_release_region(pctrl->tint_slot, i, get_order(1));  in rzg2l_gpio_irq_domain_free()
1290 				spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);  in rzg2l_gpio_irq_domain_free()
1291 				pctrl->hwirq[i] = 0;  in rzg2l_gpio_irq_domain_free()
1304 	struct gpio_chip *chip = &pctrl->gpio_chip;  in rzg2l_init_irq_valid_mask()
1308 	for (offset = 0; offset < chip->ngpio; offset++) {  in rzg2l_init_irq_valid_mask()
1322 	struct device_node *np = pctrl->dev->of_node;  in rzg2l_gpio_register()
1323 	struct gpio_chip *chip = &pctrl->gpio_chip;  in rzg2l_gpio_register()
1324 	const char *name = dev_name(pctrl->dev);  in rzg2l_gpio_register()
1333 		return -ENXIO;  in rzg2l_gpio_register()
1338 		return -EPROBE_DEFER;  in rzg2l_gpio_register()
1340 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);  in rzg2l_gpio_register()
1342 		dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");  in rzg2l_gpio_register()
1347 	    of_args.args[2] != pctrl->data->n_port_pins) {  in rzg2l_gpio_register()
1348 		dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");  in rzg2l_gpio_register()
1349 		return -EINVAL;  in rzg2l_gpio_register()
1352 	chip->names = pctrl->data->port_pins;  in rzg2l_gpio_register()
1353 	chip->request = rzg2l_gpio_request;  in rzg2l_gpio_register()
1354 	chip->free = rzg2l_gpio_free;  in rzg2l_gpio_register()
1355 	chip->get_direction = rzg2l_gpio_get_direction;  in rzg2l_gpio_register()
1356 	chip->direction_input = rzg2l_gpio_direction_input;  in rzg2l_gpio_register()
1357 	chip->direction_output = rzg2l_gpio_direction_output;  in rzg2l_gpio_register()
1358 	chip->get = rzg2l_gpio_get;  in rzg2l_gpio_register()
1359 	chip->set = rzg2l_gpio_set;  in rzg2l_gpio_register()
1360 	chip->label = name;  in rzg2l_gpio_register()
1361 	chip->parent = pctrl->dev;  in rzg2l_gpio_register()
1362 	chip->owner = THIS_MODULE;  in rzg2l_gpio_register()
1363 	chip->base = -1;  in rzg2l_gpio_register()
1364 	chip->ngpio = of_args.args[2];  in rzg2l_gpio_register()
1366 	girq = &chip->irq;  in rzg2l_gpio_register()
1368 	girq->fwnode = of_node_to_fwnode(np);  in rzg2l_gpio_register()
1369 	girq->parent_domain = parent_domain;  in rzg2l_gpio_register()
1370 	girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;  in rzg2l_gpio_register()
1371 	girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;  in rzg2l_gpio_register()
1372 	girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;  in rzg2l_gpio_register()
1373 	girq->init_valid_mask = rzg2l_init_irq_valid_mask;  in rzg2l_gpio_register()
1375 	pctrl->gpio_range.id = 0;  in rzg2l_gpio_register()
1376 	pctrl->gpio_range.pin_base = 0;  in rzg2l_gpio_register()
1377 	pctrl->gpio_range.base = 0;  in rzg2l_gpio_register()
1378 	pctrl->gpio_range.npins = chip->ngpio;  in rzg2l_gpio_register()
1379 	pctrl->gpio_range.name = chip->label;  in rzg2l_gpio_register()
1380 	pctrl->gpio_range.gc = chip;  in rzg2l_gpio_register()
1381 	ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);  in rzg2l_gpio_register()
1383 		dev_err(pctrl->dev, "failed to add GPIO controller\n");  in rzg2l_gpio_register()
1387 	dev_dbg(pctrl->dev, "Registered gpio controller\n");  in rzg2l_gpio_register()
1399 	pctrl->desc.name = DRV_NAME;  in rzg2l_pinctrl_register()
1400 	pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;  in rzg2l_pinctrl_register()
1401 	pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;  in rzg2l_pinctrl_register()
1402 	pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;  in rzg2l_pinctrl_register()
1403 	pctrl->desc.confops = &rzg2l_pinctrl_confops;  in rzg2l_pinctrl_register()
1404 	pctrl->desc.owner = THIS_MODULE;  in rzg2l_pinctrl_register()
1406 	pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);  in rzg2l_pinctrl_register()
1408 		return -ENOMEM;  in rzg2l_pinctrl_register()
1410 	pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,  in rzg2l_pinctrl_register()
1413 		return -ENOMEM;  in rzg2l_pinctrl_register()
1415 	pctrl->pins = pins;  in rzg2l_pinctrl_register()
1416 	pctrl->desc.pins = pins;  in rzg2l_pinctrl_register()
1418 	for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {  in rzg2l_pinctrl_register()
1420 		pins[i].name = pctrl->data->port_pins[i];  in rzg2l_pinctrl_register()
1423 		pin_data[i] = pctrl->data->port_pin_configs[j];  in rzg2l_pinctrl_register()
1427 	for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {  in rzg2l_pinctrl_register()
1428 		unsigned int index = pctrl->data->n_port_pins + i;  in rzg2l_pinctrl_register()
1431 		pins[index].name = pctrl->data->dedicated_pins[i].name;  in rzg2l_pinctrl_register()
1432 		pin_data[index] = pctrl->data->dedicated_pins[i].config;  in rzg2l_pinctrl_register()
1436 	ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,  in rzg2l_pinctrl_register()
1437 					     &pctrl->pctl);  in rzg2l_pinctrl_register()
1439 		dev_err(pctrl->dev, "pinctrl registration failed\n");  in rzg2l_pinctrl_register()
1443 	ret = pinctrl_enable(pctrl->pctl);  in rzg2l_pinctrl_register()
1445 		dev_err(pctrl->dev, "pinctrl enable failed\n");  in rzg2l_pinctrl_register()
1451 		dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);  in rzg2l_pinctrl_register()
1468 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);  in rzg2l_pinctrl_probe()
1470 		return -ENOMEM;  in rzg2l_pinctrl_probe()
1472 	pctrl->dev = &pdev->dev;  in rzg2l_pinctrl_probe()
1474 	pctrl->data = of_device_get_match_data(&pdev->dev);  in rzg2l_pinctrl_probe()
1475 	if (!pctrl->data)  in rzg2l_pinctrl_probe()
1476 		return -EINVAL;  in rzg2l_pinctrl_probe()
1478 	pctrl->base = devm_platform_ioremap_resource(pdev, 0);  in rzg2l_pinctrl_probe()
1479 	if (IS_ERR(pctrl->base))  in rzg2l_pinctrl_probe()
1480 		return PTR_ERR(pctrl->base);  in rzg2l_pinctrl_probe()
1482 	pctrl->clk = devm_clk_get(pctrl->dev, NULL);  in rzg2l_pinctrl_probe()
1483 	if (IS_ERR(pctrl->clk)) {  in rzg2l_pinctrl_probe()
1484 		ret = PTR_ERR(pctrl->clk);  in rzg2l_pinctrl_probe()
1485 		dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);  in rzg2l_pinctrl_probe()
1489 	spin_lock_init(&pctrl->lock);  in rzg2l_pinctrl_probe()
1490 	spin_lock_init(&pctrl->bitmap_lock);  in rzg2l_pinctrl_probe()
1494 	ret = clk_prepare_enable(pctrl->clk);  in rzg2l_pinctrl_probe()
1496 		dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret);  in rzg2l_pinctrl_probe()
1500 	ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable,  in rzg2l_pinctrl_probe()
1501 				       pctrl->clk);  in rzg2l_pinctrl_probe()
1503 		dev_err(pctrl->dev,  in rzg2l_pinctrl_probe()
1513 	dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);  in rzg2l_pinctrl_probe()
1536 		.compatible = "renesas,r9a07g043-pinctrl",
1540 		.compatible = "renesas,r9a07g044-pinctrl",
1560 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");