Lines Matching +full:can +full:- +full:r8a7791
1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (C) 2009 - 2012 Paul Mundt
11 #define DRV_NAME "sh-pfc"
48 return -EINVAL; in sh_pfc_map_resources()
55 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows), in sh_pfc_map_resources()
58 return -ENOMEM; in sh_pfc_map_resources()
60 pfc->num_windows = num_windows; in sh_pfc_map_resources()
61 pfc->windows = windows; in sh_pfc_map_resources()
64 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs), in sh_pfc_map_resources()
67 return -ENOMEM; in sh_pfc_map_resources()
69 pfc->num_irqs = num_irqs; in sh_pfc_map_resources()
70 pfc->irqs = irqs; in sh_pfc_map_resources()
75 windows->virt = devm_platform_get_and_ioremap_resource(pdev, i, &res); in sh_pfc_map_resources()
76 if (IS_ERR(windows->virt)) in sh_pfc_map_resources()
77 return -ENOMEM; in sh_pfc_map_resources()
78 windows->phys = res->start; in sh_pfc_map_resources()
79 windows->size = resource_size(res); in sh_pfc_map_resources()
95 for (i = 0; i < pfc->num_windows; i++) { in sh_pfc_phys_to_virt()
96 window = pfc->windows + i; in sh_pfc_phys_to_virt()
98 if (address < window->phys) in sh_pfc_phys_to_virt()
101 if (address >= (window->phys + window->size)) in sh_pfc_phys_to_virt()
104 return window->virt + (address - window->phys); in sh_pfc_phys_to_virt()
116 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { in sh_pfc_get_pin_index()
117 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; in sh_pfc_get_pin_index()
119 if (pin <= range->end) in sh_pfc_get_pin_index()
120 return pin >= range->start in sh_pfc_get_pin_index()
121 ? offset + pin - range->start : -1; in sh_pfc_get_pin_index()
123 offset += range->end - range->start + 1; in sh_pfc_get_pin_index()
126 return -EINVAL; in sh_pfc_get_pin_index()
131 if (enum_id < r->begin) in sh_pfc_enum_in_range()
134 if (enum_id > r->end) in sh_pfc_enum_in_range()
182 if (!pfc->info->unlock_reg) in sh_pfc_unlock_reg()
185 if (pfc->info->unlock_reg >= 0x80000000UL) in sh_pfc_unlock_reg()
186 unlock = pfc->info->unlock_reg; in sh_pfc_unlock_reg()
189 unlock = reg & ~pfc->info->unlock_reg; in sh_pfc_unlock_reg()
208 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); in sh_pfc_config_reg_helper()
210 if (crp->field_width) { in sh_pfc_config_reg_helper()
211 *maskp = (1 << crp->field_width) - 1; in sh_pfc_config_reg_helper()
212 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); in sh_pfc_config_reg_helper()
214 *maskp = (1 << crp->var_field_width[in_pos]) - 1; in sh_pfc_config_reg_helper()
215 *posp = crp->reg_width; in sh_pfc_config_reg_helper()
217 *posp -= abs(crp->var_field_width[k]); in sh_pfc_config_reg_helper()
231 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " in sh_pfc_write_config_reg()
233 crp->reg, value, field, crp->reg_width, hweight32(mask)); in sh_pfc_write_config_reg()
238 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); in sh_pfc_write_config_reg()
242 sh_pfc_unlock_reg(pfc, crp->reg, data); in sh_pfc_write_config_reg()
243 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); in sh_pfc_write_config_reg()
254 pfc->info->cfg_regs + k; in sh_pfc_get_config_reg()
255 unsigned int r_width = config_reg->reg_width; in sh_pfc_get_config_reg()
256 unsigned int f_width = config_reg->field_width; in sh_pfc_get_config_reg()
272 curr_width = abs(config_reg->var_field_width[m]); in sh_pfc_get_config_reg()
273 if (config_reg->var_field_width[m] < 0) in sh_pfc_get_config_reg()
279 if (config_reg->enum_ids[pos + n] == enum_id) { in sh_pfc_get_config_reg()
291 return -EINVAL; in sh_pfc_get_config_reg()
297 const u16 *data = pfc->info->pinmux_data; in sh_pfc_mark_to_enum()
305 for (k = 0; k < pfc->info->pinmux_data_size; k++) { in sh_pfc_mark_to_enum()
312 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", in sh_pfc_mark_to_enum()
314 return -EINVAL; in sh_pfc_mark_to_enum()
330 range = &pfc->info->output; in sh_pfc_config_mux()
334 range = &pfc->info->input; in sh_pfc_config_mux()
339 return -EINVAL; in sh_pfc_config_mux()
362 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); in sh_pfc_config_mux()
370 /* Input/output types can only modify fields in sh_pfc_config_mux()
377 * input-only or output-only pins without in sh_pfc_config_mux()
380 if (in_range && enum_id == range->force) in sh_pfc_config_mux()
405 if (pfc->info->pins[0].pin == (u16)-1) { in sh_pfc_init_ranges()
406 /* Pin number -1 denotes that the SoC doesn't report pin numbers in sh_pfc_init_ranges()
410 pfc->nr_ranges = 1; in sh_pfc_init_ranges()
411 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges), in sh_pfc_init_ranges()
413 if (pfc->ranges == NULL) in sh_pfc_init_ranges()
414 return -ENOMEM; in sh_pfc_init_ranges()
416 pfc->ranges->start = 0; in sh_pfc_init_ranges()
417 pfc->ranges->end = pfc->info->nr_pins - 1; in sh_pfc_init_ranges()
418 pfc->nr_gpio_pins = pfc->info->nr_pins; in sh_pfc_init_ranges()
427 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { in sh_pfc_init_ranges()
428 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) in sh_pfc_init_ranges()
432 pfc->nr_ranges = nr_ranges; in sh_pfc_init_ranges()
433 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges), in sh_pfc_init_ranges()
435 if (pfc->ranges == NULL) in sh_pfc_init_ranges()
436 return -ENOMEM; in sh_pfc_init_ranges()
438 range = pfc->ranges; in sh_pfc_init_ranges()
439 range->start = pfc->info->pins[0].pin; in sh_pfc_init_ranges()
441 for (i = 1; i < pfc->info->nr_pins; ++i) { in sh_pfc_init_ranges()
442 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) in sh_pfc_init_ranges()
445 range->end = pfc->info->pins[i-1].pin; in sh_pfc_init_ranges()
446 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) in sh_pfc_init_ranges()
447 pfc->nr_gpio_pins = range->end + 1; in sh_pfc_init_ranges()
450 range->start = pfc->info->pins[i].pin; in sh_pfc_init_ranges()
453 range->end = pfc->info->pins[i-1].pin; in sh_pfc_init_ranges()
454 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) in sh_pfc_init_ranges()
455 pfc->nr_gpio_pins = range->end + 1; in sh_pfc_init_ranges()
464 .compatible = "renesas,pfc-emev2",
470 .compatible = "renesas,pfc-r8a73a4",
476 .compatible = "renesas,pfc-r8a7740",
482 .compatible = "renesas,pfc-r8a7742",
488 .compatible = "renesas,pfc-r8a7743",
494 .compatible = "renesas,pfc-r8a7744",
500 .compatible = "renesas,pfc-r8a7745",
506 .compatible = "renesas,pfc-r8a77470",
512 .compatible = "renesas,pfc-r8a774a1",
518 .compatible = "renesas,pfc-r8a774b1",
524 .compatible = "renesas,pfc-r8a774c0",
530 .compatible = "renesas,pfc-r8a774e1",
536 .compatible = "renesas,pfc-r8a7778",
542 .compatible = "renesas,pfc-r8a7779",
548 .compatible = "renesas,pfc-r8a7790",
554 .compatible = "renesas,pfc-r8a7791",
560 .compatible = "renesas,pfc-r8a7792",
566 .compatible = "renesas,pfc-r8a7793",
572 .compatible = "renesas,pfc-r8a7794",
579 * R-Car H3 ES1.x is matched using soc_device_match() instead.
583 .compatible = "renesas,pfc-r8a7795",
589 .compatible = "renesas,pfc-r8a7795",
595 .compatible = "renesas,pfc-r8a7796",
601 .compatible = "renesas,pfc-r8a77961",
607 .compatible = "renesas,pfc-r8a77965",
613 .compatible = "renesas,pfc-r8a77970",
619 .compatible = "renesas,pfc-r8a77980",
625 .compatible = "renesas,pfc-r8a77990",
631 .compatible = "renesas,pfc-r8a77995",
637 .compatible = "renesas,pfc-r8a779a0",
643 .compatible = "renesas,pfc-r8a779f0",
649 .compatible = "renesas,pfc-r8a779g0",
655 .compatible = "renesas,pfc-sh73a0",
670 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg); in sh_pfc_save_reg()
675 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]); in sh_pfc_restore_reg()
683 if (pfc->info->cfg_regs) in sh_pfc_walk_regs()
684 for (i = 0; pfc->info->cfg_regs[i].reg; i++) in sh_pfc_walk_regs()
685 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++); in sh_pfc_walk_regs()
687 if (pfc->info->drive_regs) in sh_pfc_walk_regs()
688 for (i = 0; pfc->info->drive_regs[i].reg; i++) in sh_pfc_walk_regs()
689 do_reg(pfc, pfc->info->drive_regs[i].reg, n++); in sh_pfc_walk_regs()
691 if (pfc->info->bias_regs) in sh_pfc_walk_regs()
692 for (i = 0; pfc->info->bias_regs[i].puen || in sh_pfc_walk_regs()
693 pfc->info->bias_regs[i].pud; i++) { in sh_pfc_walk_regs()
694 if (pfc->info->bias_regs[i].puen) in sh_pfc_walk_regs()
695 do_reg(pfc, pfc->info->bias_regs[i].puen, n++); in sh_pfc_walk_regs()
696 if (pfc->info->bias_regs[i].pud) in sh_pfc_walk_regs()
697 do_reg(pfc, pfc->info->bias_regs[i].pud, n++); in sh_pfc_walk_regs()
700 if (pfc->info->ioctrl_regs) in sh_pfc_walk_regs()
701 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++) in sh_pfc_walk_regs()
702 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++); in sh_pfc_walk_regs()
711 /* This is the best we can do to check for the presence of PSCI */ in sh_pfc_suspend_init()
719 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n, in sh_pfc_suspend_init()
720 sizeof(*pfc->saved_regs), in sh_pfc_suspend_init()
722 if (!pfc->saved_regs) in sh_pfc_suspend_init()
723 return -ENOMEM; in sh_pfc_suspend_init()
725 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n); in sh_pfc_suspend_init()
733 if (pfc->saved_regs) in sh_pfc_suspend_noirq()
742 if (pfc->saved_regs) in sh_pfc_resume_noirq()
841 return -EINVAL; in sh_pfc_check_enum()
868 const char *drvname = info->name; in sh_pfc_find_pin()
874 for (i = 0; i < info->nr_pins; i++) { in sh_pfc_find_pin()
875 if (pin == info->pins[i].pin) in sh_pfc_find_pin()
876 return &info->pins[i]; in sh_pfc_find_pin()
889 sh_pfc_check_reg(drvname, cfg_reg->reg, in sh_pfc_check_cfg_reg()
890 GENMASK(cfg_reg->reg_width - 1, 0)); in sh_pfc_check_cfg_reg()
892 if (cfg_reg->field_width) { in sh_pfc_check_cfg_reg()
893 fw = cfg_reg->field_width; in sh_pfc_check_cfg_reg()
894 n = (cfg_reg->reg_width / fw) << fw; in sh_pfc_check_cfg_reg()
896 if (is0s(&cfg_reg->enum_ids[i], 1 << fw)) in sh_pfc_check_cfg_reg()
900 if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw) in sh_pfc_check_cfg_reg()
901 sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n", in sh_pfc_check_cfg_reg()
902 cfg_reg->reg); in sh_pfc_check_cfg_reg()
908 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) { in sh_pfc_check_cfg_reg()
910 rw += -fw; in sh_pfc_check_cfg_reg()
912 if (is0s(&cfg_reg->enum_ids[n], 1 << fw)) in sh_pfc_check_cfg_reg()
913 sh_pfc_warn("reg 0x%x: field [%u:%u] can be described as reserved\n", in sh_pfc_check_cfg_reg()
914 cfg_reg->reg, rw, rw + fw - 1); in sh_pfc_check_cfg_reg()
920 if (rw != cfg_reg->reg_width) in sh_pfc_check_cfg_reg()
922 cfg_reg->reg, rw, cfg_reg->reg_width); in sh_pfc_check_cfg_reg()
924 if (n != cfg_reg->nr_enum_ids) in sh_pfc_check_cfg_reg()
926 cfg_reg->reg, cfg_reg->nr_enum_ids, n); in sh_pfc_check_cfg_reg()
929 sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n); in sh_pfc_check_cfg_reg()
935 const char *drvname = info->name; in sh_pfc_check_drive_reg()
939 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) { in sh_pfc_check_drive_reg()
940 const struct pinmux_drive_reg_field *field = &drive->fields[i]; in sh_pfc_check_drive_reg()
942 if (!field->pin && !field->offset && !field->size) in sh_pfc_check_drive_reg()
945 sh_pfc_check_reg(info->name, drive->reg, in sh_pfc_check_drive_reg()
946 GENMASK(field->offset + field->size - 1, in sh_pfc_check_drive_reg()
947 field->offset)); in sh_pfc_check_drive_reg()
949 pin = sh_pfc_find_pin(info, drive->reg, field->pin); in sh_pfc_check_drive_reg()
950 if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH)) in sh_pfc_check_drive_reg()
952 drive->reg, i, pin->name); in sh_pfc_check_drive_reg()
959 const char *drvname = info->name; in sh_pfc_check_bias_reg()
964 for (i = 0, bits = 0; i < ARRAY_SIZE(bias->pins); i++) in sh_pfc_check_bias_reg()
965 if (bias->pins[i] != SH_PFC_PIN_NONE) in sh_pfc_check_bias_reg()
968 if (bias->puen) in sh_pfc_check_bias_reg()
969 sh_pfc_check_reg(info->name, bias->puen, bits); in sh_pfc_check_bias_reg()
970 if (bias->pud) in sh_pfc_check_bias_reg()
971 sh_pfc_check_reg(info->name, bias->pud, bits); in sh_pfc_check_bias_reg()
972 for (i = 0; i < ARRAY_SIZE(bias->pins); i++) { in sh_pfc_check_bias_reg()
973 pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]); in sh_pfc_check_bias_reg()
977 if (bias->puen && bias->pud) { in sh_pfc_check_bias_reg()
979 * Pull-enable and pull-up/down control registers in sh_pfc_check_bias_reg()
980 * As some SoCs have pins that support only pull-up in sh_pfc_check_bias_reg()
981 * or pull-down, we just check for one of them in sh_pfc_check_bias_reg()
983 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN)) in sh_pfc_check_bias_reg()
985 bias->puen, i, pin->name); in sh_pfc_check_bias_reg()
986 } else if (bias->puen) { in sh_pfc_check_bias_reg()
987 /* Pull-up control register only */ in sh_pfc_check_bias_reg()
988 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP)) in sh_pfc_check_bias_reg()
990 bias->puen, i, pin->name); in sh_pfc_check_bias_reg()
991 } else if (bias->pud) { in sh_pfc_check_bias_reg()
992 /* Pull-down control register only */ in sh_pfc_check_bias_reg()
993 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN)) in sh_pfc_check_bias_reg()
995 bias->pud, i, pin->name); in sh_pfc_check_bias_reg()
1007 if (same_name(a->name, b->name)) in sh_pfc_compare_groups()
1008 sh_pfc_err("group %s: name conflict\n", a->name); in sh_pfc_compare_groups()
1010 if (a->nr_pins > b->nr_pins) in sh_pfc_compare_groups()
1013 len = a->nr_pins * sizeof(a->pins[0]); in sh_pfc_compare_groups()
1014 for (i = 0; i <= b->nr_pins - a->nr_pins; i++) { in sh_pfc_compare_groups()
1015 if (a->pins == b->pins + i || a->mux == b->mux + i || in sh_pfc_compare_groups()
1016 memcmp(a->pins, b->pins + i, len) || in sh_pfc_compare_groups()
1017 memcmp(a->mux, b->mux + i, len)) in sh_pfc_compare_groups()
1020 if (a->nr_pins == b->nr_pins) in sh_pfc_compare_groups()
1021 sh_pfc_warn("group %s can be an alias for %s\n", in sh_pfc_compare_groups()
1022 a->name, b->name); in sh_pfc_compare_groups()
1024 sh_pfc_warn("group %s is a subset of %s\n", a->name, in sh_pfc_compare_groups()
1025 b->name); in sh_pfc_compare_groups()
1031 const struct pinmux_drive_reg *drive_regs = info->drive_regs; in sh_pfc_check_info()
1032 #define drive_nfields ARRAY_SIZE(drive_regs->fields) in sh_pfc_check_info()
1037 const struct pinmux_bias_reg *bias_regs = info->bias_regs; in sh_pfc_check_info()
1038 #define bias_npins ARRAY_SIZE(bias_regs->pins) in sh_pfc_check_info()
1044 const char *drvname = info->name; in sh_pfc_check_info()
1056 for (i = 0; i < info->nr_pins; i++) { in sh_pfc_check_info()
1057 const struct sh_pfc_pin *pin = &info->pins[i]; in sh_pfc_check_info()
1060 if (!pin->name) { in sh_pfc_check_info()
1065 const struct sh_pfc_pin *pin2 = &info->pins[j]; in sh_pfc_check_info()
1067 if (same_name(pin->name, pin2->name)) in sh_pfc_check_info()
1069 pin->name); in sh_pfc_check_info()
1071 if (pin->pin != (u16)-1 && pin->pin == pin2->pin) in sh_pfc_check_info()
1073 pin->name, pin2->name, pin->pin); in sh_pfc_check_info()
1075 if (pin->enum_id && pin->enum_id == pin2->enum_id) in sh_pfc_check_info()
1077 pin->name, pin2->name, in sh_pfc_check_info()
1078 pin->enum_id); in sh_pfc_check_info()
1081 if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) { in sh_pfc_check_info()
1082 if (!info->ops || !info->ops->get_bias || in sh_pfc_check_info()
1083 !info->ops->set_bias) in sh_pfc_check_info()
1087 (!info->ops || !info->ops->pin_to_portcr)) in sh_pfc_check_info()
1091 if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) { in sh_pfc_check_info()
1093 rcar_pin_to_bias_reg(info, pin->pin, &x); in sh_pfc_check_info()
1096 ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) && in sh_pfc_check_info()
1097 !bias_reg->puen)) in sh_pfc_check_info()
1099 pin->name); in sh_pfc_check_info()
1102 ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) && in sh_pfc_check_info()
1103 !bias_reg->pud)) in sh_pfc_check_info()
1105 pin->name); in sh_pfc_check_info()
1108 if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) { in sh_pfc_check_info()
1118 if (drive_field(j).pin == pin->pin) in sh_pfc_check_info()
1124 pin->name); in sh_pfc_check_info()
1128 if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) { in sh_pfc_check_info()
1129 if (!info->ops || !info->ops->pin_to_pocctrl) in sh_pfc_check_info()
1131 else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0) in sh_pfc_check_info()
1133 pin->name); in sh_pfc_check_info()
1134 } else if (info->ops && info->ops->pin_to_pocctrl && in sh_pfc_check_info()
1135 info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) { in sh_pfc_check_info()
1137 pin->name); in sh_pfc_check_info()
1142 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL); in sh_pfc_check_info()
1146 for (i = 0; i < info->nr_functions; i++) { in sh_pfc_check_info()
1147 const struct sh_pfc_function *func = &info->functions[i]; in sh_pfc_check_info()
1149 if (!func->name) { in sh_pfc_check_info()
1154 if (same_name(func->name, info->functions[j].name)) in sh_pfc_check_info()
1156 func->name); in sh_pfc_check_info()
1158 for (j = 0; j < func->nr_groups; j++) { in sh_pfc_check_info()
1159 for (k = 0; k < info->nr_groups; k++) { in sh_pfc_check_info()
1160 if (same_name(func->groups[j], in sh_pfc_check_info()
1161 info->groups[k].name)) { in sh_pfc_check_info()
1167 if (k == info->nr_groups) in sh_pfc_check_info()
1169 func->name, func->groups[j]); in sh_pfc_check_info()
1173 for (i = 0; i < info->nr_groups; i++) { in sh_pfc_check_info()
1174 const struct sh_pfc_pin_group *group = &info->groups[i]; in sh_pfc_check_info()
1176 if (!group->name) { in sh_pfc_check_info()
1181 sh_pfc_compare_groups(drvname, group, &info->groups[j]); in sh_pfc_check_info()
1184 sh_pfc_err("orphan group %s\n", group->name); in sh_pfc_check_info()
1187 group->name, refcnts[i]); in sh_pfc_check_info()
1193 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++) in sh_pfc_check_info()
1194 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]); in sh_pfc_check_info()
1239 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++) in sh_pfc_check_info()
1240 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX); in sh_pfc_check_info()
1243 for (i = 0; info->data_regs && info->data_regs[i].reg; i++) { in sh_pfc_check_info()
1244 sh_pfc_check_reg(drvname, info->data_regs[i].reg, in sh_pfc_check_info()
1245 GENMASK(info->data_regs[i].reg_width - 1, 0)); in sh_pfc_check_info()
1246 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg, in sh_pfc_check_info()
1247 info->data_regs[i].enum_ids, in sh_pfc_check_info()
1248 info->data_regs[i].reg_width); in sh_pfc_check_info()
1253 for (i = 0; i < info->nr_func_gpios; i++) { in sh_pfc_check_info()
1254 const struct pinmux_func *func = &info->func_gpios[i]; in sh_pfc_check_info()
1256 if (!func->name) { in sh_pfc_check_info()
1261 if (same_name(func->name, info->func_gpios[j].name)) in sh_pfc_check_info()
1263 func->name); in sh_pfc_check_info()
1265 if (sh_pfc_check_enum(drvname, func->enum_id)) in sh_pfc_check_info()
1266 sh_pfc_err("%s enum_id %u conflict\n", func->name, in sh_pfc_check_info()
1267 func->enum_id); in sh_pfc_check_info()
1277 !of_find_matching_node(NULL, pdrv->driver.of_match_table)) in sh_pfc_check_driver()
1292 for (i = 0; pdrv->id_table[i].name[0]; i++) in sh_pfc_check_driver()
1293 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data); in sh_pfc_check_driver()
1296 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++) in sh_pfc_check_driver()
1297 sh_pfc_check_info(pdrv->driver.of_match_table[i].data); in sh_pfc_check_driver()
1327 return match->data; in sh_pfc_quirk_match()
1341 if (pdev->dev.of_node) { in sh_pfc_probe()
1344 info = of_device_get_match_data(&pdev->dev); in sh_pfc_probe()
1347 info = (const void *)platform_get_device_id(pdev)->driver_data; in sh_pfc_probe()
1349 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); in sh_pfc_probe()
1351 return -ENOMEM; in sh_pfc_probe()
1353 pfc->info = info; in sh_pfc_probe()
1354 pfc->dev = &pdev->dev; in sh_pfc_probe()
1360 spin_lock_init(&pfc->lock); in sh_pfc_probe()
1362 if (info->ops && info->ops->init) { in sh_pfc_probe()
1363 ret = info->ops->init(pfc); in sh_pfc_probe()
1367 /* .init() may have overridden pfc->info */ in sh_pfc_probe()
1368 info = pfc->info; in sh_pfc_probe()
1401 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); in sh_pfc_probe()
1407 dev_info(pfc->dev, "%s support registered\n", info->name); in sh_pfc_probe()
1414 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1417 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1420 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1423 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1426 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1429 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1432 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1435 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1438 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1441 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1444 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1447 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },