Lines Matching full:pctrl
125 struct pinctrl_dev *pctrl; member
165 static int pm8xxx_mpp_update(struct pm8xxx_mpp *pctrl, in pm8xxx_mpp_update() argument
234 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_mpp_update()
236 dev_err(pctrl->dev, "failed to write register\n"); in pm8xxx_mpp_update()
243 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_get_groups_count() local
245 return pctrl->npins; in pm8xxx_get_groups_count()
260 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_get_group_pins() local
262 *pins = &pctrl->desc.pins[group].number; in pm8xxx_get_group_pins()
292 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_get_function_groups() local
295 *num_groups = pctrl->npins; in pm8xxx_get_function_groups()
303 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_pinmux_set_mux() local
304 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; in pm8xxx_pinmux_set_mux()
307 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_pinmux_set_mux()
323 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_pin_config_get() local
324 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_get()
373 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev); in pm8xxx_pin_config_set() local
374 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_set()
416 dev_err(pctrl->dev, in pm8xxx_pin_config_set()
423 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_pin_config_set()
445 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_direction_input() local
446 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_direction_input()
460 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_mpp_direction_input()
469 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_direction_output() local
470 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_direction_output()
486 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_mpp_direction_output()
493 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_get() local
494 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_get()
514 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_set() local
515 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_set()
519 pm8xxx_mpp_update(pctrl, pin); in pm8xxx_mpp_set()
545 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); in pm8xxx_mpp_dbg_show_one() local
546 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_mpp_dbg_show_one()
644 static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, in pm8xxx_pin_populate() argument
653 ret = regmap_read(pctrl->regmap, pin->reg, &val); in pm8xxx_pin_populate()
655 dev_err(pctrl->dev, "failed to read register\n"); in pm8xxx_pin_populate()
736 struct pm8xxx_mpp *pctrl = container_of(domain->host_data, in pm8xxx_mpp_domain_translate() local
741 fwspec->param[0] > pctrl->chip.ngpio) in pm8xxx_mpp_domain_translate()
798 struct pm8xxx_mpp *pctrl; in pm8xxx_mpp_probe() local
802 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in pm8xxx_mpp_probe()
803 if (!pctrl) in pm8xxx_mpp_probe()
806 pctrl->dev = &pdev->dev; in pm8xxx_mpp_probe()
807 pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); in pm8xxx_mpp_probe()
809 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); in pm8xxx_mpp_probe()
810 if (!pctrl->regmap) { in pm8xxx_mpp_probe()
815 pctrl->desc = pm8xxx_pinctrl_desc; in pm8xxx_mpp_probe()
816 pctrl->desc.npins = pctrl->npins; in pm8xxx_mpp_probe()
819 pctrl->desc.npins, in pm8xxx_mpp_probe()
826 pctrl->desc.npins, in pm8xxx_mpp_probe()
832 for (i = 0; i < pctrl->desc.npins; i++) { in pm8xxx_mpp_probe()
835 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); in pm8xxx_mpp_probe()
843 pctrl->desc.pins = pins; in pm8xxx_mpp_probe()
845 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_mpp_bindings); in pm8xxx_mpp_probe()
846 pctrl->desc.custom_params = pm8xxx_mpp_bindings; in pm8xxx_mpp_probe()
848 pctrl->desc.custom_conf_items = pm8xxx_conf_items; in pm8xxx_mpp_probe()
851 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in pm8xxx_mpp_probe()
852 if (IS_ERR(pctrl->pctrl)) { in pm8xxx_mpp_probe()
854 return PTR_ERR(pctrl->pctrl); in pm8xxx_mpp_probe()
857 pctrl->chip = pm8xxx_mpp_template; in pm8xxx_mpp_probe()
858 pctrl->chip.base = -1; in pm8xxx_mpp_probe()
859 pctrl->chip.parent = &pdev->dev; in pm8xxx_mpp_probe()
860 pctrl->chip.of_gpio_n_cells = 2; in pm8xxx_mpp_probe()
861 pctrl->chip.label = dev_name(pctrl->dev); in pm8xxx_mpp_probe()
862 pctrl->chip.ngpio = pctrl->npins; in pm8xxx_mpp_probe()
864 parent_node = of_irq_find_parent(pctrl->dev->of_node); in pm8xxx_mpp_probe()
873 pctrl->irq.name = "ssbi-mpp"; in pm8xxx_mpp_probe()
874 pctrl->irq.irq_mask_ack = irq_chip_mask_ack_parent; in pm8xxx_mpp_probe()
875 pctrl->irq.irq_unmask = irq_chip_unmask_parent; in pm8xxx_mpp_probe()
876 pctrl->irq.irq_set_type = irq_chip_set_type_parent; in pm8xxx_mpp_probe()
877 pctrl->irq.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; in pm8xxx_mpp_probe()
879 girq = &pctrl->chip.irq; in pm8xxx_mpp_probe()
880 girq->chip = &pctrl->irq; in pm8xxx_mpp_probe()
883 girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node); in pm8xxx_mpp_probe()
893 ret = gpiochip_add_data(&pctrl->chip, pctrl); in pm8xxx_mpp_probe()
899 ret = gpiochip_add_pin_range(&pctrl->chip, in pm8xxx_mpp_probe()
900 dev_name(pctrl->dev), in pm8xxx_mpp_probe()
901 0, 0, pctrl->chip.ngpio); in pm8xxx_mpp_probe()
903 dev_err(pctrl->dev, "failed to add pin range\n"); in pm8xxx_mpp_probe()
907 platform_set_drvdata(pdev, pctrl); in pm8xxx_mpp_probe()
914 gpiochip_remove(&pctrl->chip); in pm8xxx_mpp_probe()
921 struct pm8xxx_mpp *pctrl = platform_get_drvdata(pdev); in pm8xxx_mpp_remove() local
923 gpiochip_remove(&pctrl->chip); in pm8xxx_mpp_remove()