Lines Matching +full:pin +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pinctrl/pinconf-generic.h>
20 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
23 #include "../pinctrl-utils.h"
57 * struct pm8xxx_pin_data - dynamic configuration for a pin
61 * @mode: operating mode for the pin (input/output)
62 * @open_drain: output buffer configured as open-drain (vs push-pull)
67 * @output_strength: selector of output-strength
68 * @disable: pin disabled / configured as tristate
70 * @inverted: pin logic is inverted
97 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0},
98 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0},
103 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
126 struct pm8xxx_pin_data *pin, int bank) in pm8xxx_read_bank() argument
131 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_read_bank()
133 dev_err(pctrl->dev, "failed to select bank %d\n", bank); in pm8xxx_read_bank()
137 ret = regmap_read(pctrl->regmap, pin->reg, &val); in pm8xxx_read_bank()
139 dev_err(pctrl->dev, "failed to read register %d\n", bank); in pm8xxx_read_bank()
147 struct pm8xxx_pin_data *pin, in pm8xxx_write_bank() argument
156 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_write_bank()
158 dev_err(pctrl->dev, "failed to write register\n"); in pm8xxx_write_bank()
167 return pctrl->npins; in pm8xxx_get_groups_count()
184 *pins = &pctrl->desc.pins[group].number; in pm8xxx_get_group_pins()
217 *num_groups = pctrl->npins; in pm8xxx_get_function_groups()
226 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; in pm8xxx_pinmux_set_mux() local
229 pin->function = function; in pm8xxx_pinmux_set_mux()
230 val = pin->function << 1; in pm8xxx_pinmux_set_mux()
232 pm8xxx_write_bank(pctrl, pin, 4, val); in pm8xxx_pinmux_set_mux()
249 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_get() local
255 if (pin->bias != PM8XXX_GPIO_BIAS_NP) in pm8xxx_pin_config_get()
256 return -EINVAL; in pm8xxx_pin_config_get()
260 if (pin->bias != PM8XXX_GPIO_BIAS_PD) in pm8xxx_pin_config_get()
261 return -EINVAL; in pm8xxx_pin_config_get()
265 if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30) in pm8xxx_pin_config_get()
266 return -EINVAL; in pm8xxx_pin_config_get()
270 arg = pin->pull_up_strength; in pm8xxx_pin_config_get()
273 if (!pin->disable) in pm8xxx_pin_config_get()
274 return -EINVAL; in pm8xxx_pin_config_get()
278 if (pin->mode != PM8XXX_GPIO_MODE_INPUT) in pm8xxx_pin_config_get()
279 return -EINVAL; in pm8xxx_pin_config_get()
283 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) in pm8xxx_pin_config_get()
284 arg = pin->output_value; in pm8xxx_pin_config_get()
289 arg = pin->power_source; in pm8xxx_pin_config_get()
292 arg = pin->output_strength; in pm8xxx_pin_config_get()
295 if (pin->open_drain) in pm8xxx_pin_config_get()
296 return -EINVAL; in pm8xxx_pin_config_get()
300 if (!pin->open_drain) in pm8xxx_pin_config_get()
301 return -EINVAL; in pm8xxx_pin_config_get()
305 return -EINVAL; in pm8xxx_pin_config_get()
319 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_set() local
332 pin->bias = PM8XXX_GPIO_BIAS_NP; in pm8xxx_pin_config_set()
334 pin->disable = 0; in pm8xxx_pin_config_set()
338 pin->bias = PM8XXX_GPIO_BIAS_PD; in pm8xxx_pin_config_set()
340 pin->disable = 0; in pm8xxx_pin_config_set()
345 dev_err(pctrl->dev, "invalid pull-up strength\n"); in pm8xxx_pin_config_set()
346 return -EINVAL; in pm8xxx_pin_config_set()
348 pin->pull_up_strength = arg; in pm8xxx_pin_config_set()
351 pin->bias = pin->pull_up_strength; in pm8xxx_pin_config_set()
353 pin->disable = 0; in pm8xxx_pin_config_set()
357 pin->disable = 1; in pm8xxx_pin_config_set()
361 pin->mode = PM8XXX_GPIO_MODE_INPUT; in pm8xxx_pin_config_set()
365 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; in pm8xxx_pin_config_set()
366 pin->output_value = !!arg; in pm8xxx_pin_config_set()
370 pin->power_source = arg; in pm8xxx_pin_config_set()
375 dev_err(pctrl->dev, "invalid drive strength\n"); in pm8xxx_pin_config_set()
376 return -EINVAL; in pm8xxx_pin_config_set()
378 pin->output_strength = arg; in pm8xxx_pin_config_set()
382 pin->open_drain = 0; in pm8xxx_pin_config_set()
386 pin->open_drain = 1; in pm8xxx_pin_config_set()
390 dev_err(pctrl->dev, in pm8xxx_pin_config_set()
393 return -EINVAL; in pm8xxx_pin_config_set()
398 val = pin->power_source << 1; in pm8xxx_pin_config_set()
400 pm8xxx_write_bank(pctrl, pin, 0, val); in pm8xxx_pin_config_set()
404 val = pin->mode << 2; in pm8xxx_pin_config_set()
405 val |= pin->open_drain << 1; in pm8xxx_pin_config_set()
406 val |= pin->output_value; in pm8xxx_pin_config_set()
407 pm8xxx_write_bank(pctrl, pin, 1, val); in pm8xxx_pin_config_set()
411 val = pin->bias << 1; in pm8xxx_pin_config_set()
412 pm8xxx_write_bank(pctrl, pin, 2, val); in pm8xxx_pin_config_set()
416 val = pin->output_strength << 2; in pm8xxx_pin_config_set()
417 val |= pin->disable; in pm8xxx_pin_config_set()
418 pm8xxx_write_bank(pctrl, pin, 3, val); in pm8xxx_pin_config_set()
422 val = pin->function << 1; in pm8xxx_pin_config_set()
423 pm8xxx_write_bank(pctrl, pin, 4, val); in pm8xxx_pin_config_set()
428 if (!pin->inverted) in pm8xxx_pin_config_set()
430 pm8xxx_write_bank(pctrl, pin, 5, val); in pm8xxx_pin_config_set()
454 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_direction_input() local
457 pin->mode = PM8XXX_GPIO_MODE_INPUT; in pm8xxx_gpio_direction_input()
458 val = pin->mode << 2; in pm8xxx_gpio_direction_input()
460 pm8xxx_write_bank(pctrl, pin, 1, val); in pm8xxx_gpio_direction_input()
470 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_direction_output() local
473 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; in pm8xxx_gpio_direction_output()
474 pin->output_value = !!value; in pm8xxx_gpio_direction_output()
476 val = pin->mode << 2; in pm8xxx_gpio_direction_output()
477 val |= pin->open_drain << 1; in pm8xxx_gpio_direction_output()
478 val |= pin->output_value; in pm8xxx_gpio_direction_output()
480 pm8xxx_write_bank(pctrl, pin, 1, val); in pm8xxx_gpio_direction_output()
488 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_get() local
492 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) in pm8xxx_gpio_get()
493 return pin->output_value; in pm8xxx_gpio_get()
495 irq = chip->to_irq(chip, offset); in pm8xxx_gpio_get()
502 ret = -EINVAL; in pm8xxx_gpio_get()
510 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_set() local
513 pin->output_value = !!value; in pm8xxx_gpio_set()
515 val = pin->mode << 2; in pm8xxx_gpio_set()
516 val |= pin->open_drain << 1; in pm8xxx_gpio_set()
517 val |= pin->output_value; in pm8xxx_gpio_set()
519 pm8xxx_write_bank(pctrl, pin, 1, val); in pm8xxx_gpio_set()
526 if (chip->of_gpio_n_cells < 2) in pm8xxx_gpio_of_xlate()
527 return -EINVAL; in pm8xxx_gpio_of_xlate()
530 *flags = gpio_desc->args[1]; in pm8xxx_gpio_of_xlate()
532 return gpio_desc->args[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; in pm8xxx_gpio_of_xlate()
546 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_gpio_dbg_show_one() local
552 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", in pm8xxx_gpio_dbg_show_one()
553 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" in pm8xxx_gpio_dbg_show_one()
556 "push-pull", "open-drain" in pm8xxx_gpio_dbg_show_one()
562 seq_printf(s, " gpio%-2d:", offset + PM8XXX_GPIO_PHYSICAL_OFFSET); in pm8xxx_gpio_dbg_show_one()
563 if (pin->disable) { in pm8xxx_gpio_dbg_show_one()
564 seq_puts(s, " ---"); in pm8xxx_gpio_dbg_show_one()
566 seq_printf(s, " %-4s", modes[pin->mode]); in pm8xxx_gpio_dbg_show_one()
567 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]); in pm8xxx_gpio_dbg_show_one()
568 seq_printf(s, " VIN%d", pin->power_source); in pm8xxx_gpio_dbg_show_one()
569 seq_printf(s, " %-27s", biases[pin->bias]); in pm8xxx_gpio_dbg_show_one()
570 seq_printf(s, " %-10s", buffer_types[pin->open_drain]); in pm8xxx_gpio_dbg_show_one()
571 seq_printf(s, " %-4s", pin->output_value ? "high" : "low"); in pm8xxx_gpio_dbg_show_one()
572 seq_printf(s, " %-7s", strengths[pin->output_strength]); in pm8xxx_gpio_dbg_show_one()
573 if (pin->inverted) in pm8xxx_gpio_dbg_show_one()
580 unsigned gpio = chip->base; in pm8xxx_gpio_dbg_show()
583 for (i = 0; i < chip->ngpio; i++, gpio++) { in pm8xxx_gpio_dbg_show()
604 struct pm8xxx_pin_data *pin) in pm8xxx_pin_populate() argument
608 val = pm8xxx_read_bank(pctrl, pin, 0); in pm8xxx_pin_populate()
612 pin->power_source = (val >> 1) & 0x7; in pm8xxx_pin_populate()
614 val = pm8xxx_read_bank(pctrl, pin, 1); in pm8xxx_pin_populate()
618 pin->mode = (val >> 2) & 0x3; in pm8xxx_pin_populate()
619 pin->open_drain = !!(val & BIT(1)); in pm8xxx_pin_populate()
620 pin->output_value = val & BIT(0); in pm8xxx_pin_populate()
622 val = pm8xxx_read_bank(pctrl, pin, 2); in pm8xxx_pin_populate()
626 pin->bias = (val >> 1) & 0x7; in pm8xxx_pin_populate()
627 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30) in pm8xxx_pin_populate()
628 pin->pull_up_strength = pin->bias; in pm8xxx_pin_populate()
630 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30; in pm8xxx_pin_populate()
632 val = pm8xxx_read_bank(pctrl, pin, 3); in pm8xxx_pin_populate()
636 pin->output_strength = (val >> 2) & 0x3; in pm8xxx_pin_populate()
637 pin->disable = val & BIT(0); in pm8xxx_pin_populate()
639 val = pm8xxx_read_bank(pctrl, pin, 4); in pm8xxx_pin_populate()
643 pin->function = (val >> 1) & 0x7; in pm8xxx_pin_populate()
645 val = pm8xxx_read_bank(pctrl, pin, 5); in pm8xxx_pin_populate()
649 pin->inverted = !(val & BIT(3)); in pm8xxx_pin_populate()
655 .name = "ssbi-gpio",
667 struct pm8xxx_gpio *pctrl = container_of(domain->host_data, in pm8xxx_domain_translate()
670 if (fwspec->param_count != 2 || fwspec->param[0] < 1 || in pm8xxx_domain_translate()
671 fwspec->param[0] > pctrl->chip.ngpio) in pm8xxx_domain_translate()
672 return -EINVAL; in pm8xxx_domain_translate()
674 *hwirq = fwspec->param[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; in pm8xxx_domain_translate()
675 *type = fwspec->param[1]; in pm8xxx_domain_translate()
699 { .compatible = "qcom,pm8018-gpio", .data = (void *) 6 },
700 { .compatible = "qcom,pm8038-gpio", .data = (void *) 12 },
701 { .compatible = "qcom,pm8058-gpio", .data = (void *) 44 },
702 { .compatible = "qcom,pm8917-gpio", .data = (void *) 38 },
703 { .compatible = "qcom,pm8921-gpio", .data = (void *) 44 },
718 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in pm8xxx_gpio_probe()
720 return -ENOMEM; in pm8xxx_gpio_probe()
722 pctrl->dev = &pdev->dev; in pm8xxx_gpio_probe()
723 pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); in pm8xxx_gpio_probe()
725 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); in pm8xxx_gpio_probe()
726 if (!pctrl->regmap) { in pm8xxx_gpio_probe()
727 dev_err(&pdev->dev, "parent regmap unavailable\n"); in pm8xxx_gpio_probe()
728 return -ENXIO; in pm8xxx_gpio_probe()
731 pctrl->desc = pm8xxx_pinctrl_desc; in pm8xxx_gpio_probe()
732 pctrl->desc.npins = pctrl->npins; in pm8xxx_gpio_probe()
734 pins = devm_kcalloc(&pdev->dev, in pm8xxx_gpio_probe()
735 pctrl->desc.npins, in pm8xxx_gpio_probe()
739 return -ENOMEM; in pm8xxx_gpio_probe()
741 pin_data = devm_kcalloc(&pdev->dev, in pm8xxx_gpio_probe()
742 pctrl->desc.npins, in pm8xxx_gpio_probe()
746 return -ENOMEM; in pm8xxx_gpio_probe()
748 for (i = 0; i < pctrl->desc.npins; i++) { in pm8xxx_gpio_probe()
759 pctrl->desc.pins = pins; in pm8xxx_gpio_probe()
761 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings); in pm8xxx_gpio_probe()
762 pctrl->desc.custom_params = pm8xxx_gpio_bindings; in pm8xxx_gpio_probe()
764 pctrl->desc.custom_conf_items = pm8xxx_conf_items; in pm8xxx_gpio_probe()
767 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in pm8xxx_gpio_probe()
768 if (IS_ERR(pctrl->pctrl)) { in pm8xxx_gpio_probe()
769 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n"); in pm8xxx_gpio_probe()
770 return PTR_ERR(pctrl->pctrl); in pm8xxx_gpio_probe()
773 pctrl->chip = pm8xxx_gpio_template; in pm8xxx_gpio_probe()
774 pctrl->chip.base = -1; in pm8xxx_gpio_probe()
775 pctrl->chip.parent = &pdev->dev; in pm8xxx_gpio_probe()
776 pctrl->chip.of_gpio_n_cells = 2; in pm8xxx_gpio_probe()
777 pctrl->chip.label = dev_name(pctrl->dev); in pm8xxx_gpio_probe()
778 pctrl->chip.ngpio = pctrl->npins; in pm8xxx_gpio_probe()
780 parent_node = of_irq_find_parent(pctrl->dev->of_node); in pm8xxx_gpio_probe()
782 return -ENXIO; in pm8xxx_gpio_probe()
787 return -ENXIO; in pm8xxx_gpio_probe()
789 girq = &pctrl->chip.irq; in pm8xxx_gpio_probe()
790 girq->chip = &pm8xxx_irq_chip; in pm8xxx_gpio_probe()
791 girq->default_type = IRQ_TYPE_NONE; in pm8xxx_gpio_probe()
792 girq->handler = handle_level_irq; in pm8xxx_gpio_probe()
793 girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node); in pm8xxx_gpio_probe()
794 girq->parent_domain = parent_domain; in pm8xxx_gpio_probe()
795 girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq; in pm8xxx_gpio_probe()
796 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; in pm8xxx_gpio_probe()
797 girq->child_offset_to_irq = pm8xxx_child_offset_to_irq; in pm8xxx_gpio_probe()
798 girq->child_irq_domain_ops.translate = pm8xxx_domain_translate; in pm8xxx_gpio_probe()
800 ret = gpiochip_add_data(&pctrl->chip, pctrl); in pm8xxx_gpio_probe()
802 dev_err(&pdev->dev, "failed register gpiochip\n"); in pm8xxx_gpio_probe()
807 * For DeviceTree-supported systems, the gpio core checks the in pm8xxx_gpio_probe()
808 * pinctrl's device node for the "gpio-ranges" property. in pm8xxx_gpio_probe()
809 * If it is present, it takes care of adding the pin ranges in pm8xxx_gpio_probe()
813 * files which don't set the "gpio-ranges" property or systems that in pm8xxx_gpio_probe()
816 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in pm8xxx_gpio_probe()
817 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), in pm8xxx_gpio_probe()
818 0, 0, pctrl->chip.ngpio); in pm8xxx_gpio_probe()
820 dev_err(pctrl->dev, "failed to add pin range\n"); in pm8xxx_gpio_probe()
827 dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n"); in pm8xxx_gpio_probe()
832 gpiochip_remove(&pctrl->chip); in pm8xxx_gpio_probe()
841 gpiochip_remove(&pctrl->chip); in pm8xxx_gpio_remove()
848 .name = "qcom-ssbi-gpio",