41  * @pctrl:          pinctrl handle.
61 	struct pinctrl_dev *pctrl;  member
84 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
87 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
89 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
92 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
101 static void msm_ack_intr_status(struct msm_pinctrl *pctrl,  in MSM_ACCESSOR()
106 	msm_writel_intr_status(val, pctrl, g);  in MSM_ACCESSOR()
111 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_groups_count()  local
113 	return pctrl->soc->ngroups;  in msm_get_groups_count()
119 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_group_name()  local
121 	return pctrl->soc->groups[group].name;  in msm_get_group_name()
129 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_group_pins()  local
131 	*pins = pctrl->soc->groups[group].pins;  in msm_get_group_pins()
132 	*num_pins = pctrl->soc->groups[group].npins;  in msm_get_group_pins()
146 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_pinmux_request()  local
147 	struct gpio_chip *chip = &pctrl->chip;  in msm_pinmux_request()
154 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_functions_count()  local
156 	return pctrl->soc->nfunctions;  in msm_get_functions_count()
162 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_function_name()  local
164 	return pctrl->soc->functions[function].name;  in msm_get_function_name()
172 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_get_function_groups()  local
174 	*groups = pctrl->soc->functions[function].groups;  in msm_get_function_groups()
175 	*num_groups = pctrl->soc->functions[function].ngroups;  in msm_get_function_groups()
183 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_pinmux_set_mux()  local
184 	struct gpio_chip *gc = &pctrl->chip;  in msm_pinmux_set_mux()
187 	unsigned int gpio_func = pctrl->soc->gpio_func;  in msm_pinmux_set_mux()
188 	unsigned int egpio_func = pctrl->soc->egpio_func;  in msm_pinmux_set_mux()
194 	g = &pctrl->soc->groups[group];  in msm_pinmux_set_mux()
216 	    !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))  in msm_pinmux_set_mux()
219 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_pinmux_set_mux()
221 	val = msm_readl_ctl(pctrl, g);  in msm_pinmux_set_mux()
230 	    !test_and_set_bit(group, pctrl->ever_gpio)) {  in msm_pinmux_set_mux()
231 		u32 io_val = msm_readl_io(pctrl, g);  in msm_pinmux_set_mux()
235 				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
238 				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
253 	msm_writel_ctl(val, pctrl, g);  in msm_pinmux_set_mux()
255 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_pinmux_set_mux()
258 	    test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {  in msm_pinmux_set_mux()
263 		if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_pinmux_set_mux()
266 			msm_ack_intr_status(pctrl, g);  in msm_pinmux_set_mux()
278 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_pinmux_request_gpio()  local
279 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];  in msm_pinmux_request_gpio()
285 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);  in msm_pinmux_request_gpio()
297 static int msm_config_reg(struct msm_pinctrl *pctrl,  in msm_config_reg()  argument
347 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_config_group_get()  local
355 	g = &pctrl->soc->groups[group];  in msm_config_group_get()
357 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_get()
361 	val = msm_readl_ctl(pctrl, g);  in msm_config_group_get()
377 		if (pctrl->soc->pull_no_keeper)  in msm_config_group_get()
385 		if (pctrl->soc->pull_no_keeper)  in msm_config_group_get()
406 		val = msm_readl_io(pctrl, g);  in msm_config_group_get()
430 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);  in msm_config_group_set()  local
440 	g = &pctrl->soc->groups[group];  in msm_config_group_set()
446 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_set()
459 			if (pctrl->soc->pull_no_keeper)  in msm_config_group_set()
465 			if (pctrl->soc->pull_no_keeper)  in msm_config_group_set()
482 			raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_config_group_set()
483 			val = msm_readl_io(pctrl, g);  in msm_config_group_set()
488 			msm_writel_io(val, pctrl, g);  in msm_config_group_set()
489 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_config_group_set()
499 			dev_err(pctrl->dev, "Unsupported config parameter: %x\n",  in msm_config_group_set()
506 			dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);  in msm_config_group_set()
510 		raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_config_group_set()
511 		val = msm_readl_ctl(pctrl, g);  in msm_config_group_set()
514 		msm_writel_ctl(val, pctrl, g);  in msm_config_group_set()
515 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_config_group_set()
530 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_direction_input()  local
534 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_input()
536 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_direction_input()
538 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_input()
540 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_input()
542 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_direction_input()
550 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_direction_output()  local
554 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_output()
556 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_direction_output()
558 	val = msm_readl_io(pctrl, g);  in msm_gpio_direction_output()
563 	msm_writel_io(val, pctrl, g);  in msm_gpio_direction_output()
565 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_output()
567 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_output()
569 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_direction_output()
576 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_get_direction()  local
580 	g = &pctrl->soc->groups[offset];  in msm_gpio_get_direction()
582 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_get_direction()
591 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_get()  local
594 	g = &pctrl->soc->groups[offset];  in msm_gpio_get()
596 	val = msm_readl_io(pctrl, g);  in msm_gpio_get()
603 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_set()  local
607 	g = &pctrl->soc->groups[offset];  in msm_gpio_set()
609 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_set()
611 	val = msm_readl_io(pctrl, g);  in msm_gpio_set()
616 	msm_writel_io(val, pctrl, g);  in msm_gpio_set()
618 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_set()
631 	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);  in msm_gpio_dbg_show_one()  local
656 	g = &pctrl->soc->groups[offset];  in msm_gpio_dbg_show_one()
657 	ctl_reg = msm_readl_ctl(pctrl, g);  in msm_gpio_dbg_show_one()
658 	io_reg = msm_readl_io(pctrl, g);  in msm_gpio_dbg_show_one()
665 	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))  in msm_gpio_dbg_show_one()
681 	if (pctrl->soc->pull_no_keeper)  in msm_gpio_dbg_show_one()
705 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_init_valid_mask()  local
708 	const int *reserved = pctrl->soc->reserved_gpios;  in msm_gpio_init_valid_mask()
716 				dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");  in msm_gpio_init_valid_mask()
726 	len = ret = device_property_count_u16(pctrl->dev, "gpios");  in msm_gpio_init_valid_mask()
737 	ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);  in msm_gpio_init_valid_mask()
739 		dev_err(pctrl->dev, "could not read list of GPIOs\n");  in msm_gpio_init_valid_mask()
783 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,  in msm_gpio_update_dual_edge_pos()  argument
792 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
794 		pol = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_update_dual_edge_pos()
796 		msm_writel_intr_cfg(pol, pctrl, g);  in msm_gpio_update_dual_edge_pos()
798 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
799 		intstat = msm_readl_intr_status(pctrl, g);  in msm_gpio_update_dual_edge_pos()
803 	dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",  in msm_gpio_update_dual_edge_pos()
810 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_mask()  local
818 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_mask()
821 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_mask()
823 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_mask()
825 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_mask()
850 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_mask()
852 	clear_bit(d->hwirq, pctrl->enabled_irqs);  in msm_gpio_irq_mask()
854 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_mask()
860 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_unmask()  local
868 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_unmask()
871 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_unmask()
873 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_unmask()
875 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_unmask()
878 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_unmask()
880 	set_bit(d->hwirq, pctrl->enabled_irqs);  in msm_gpio_irq_unmask()
882 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_unmask()
888 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_enable()  local
895 	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_enable()
902 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_disable()  local
907 	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_disable()
925 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_update_dual_edge_parent()  local
926 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_update_dual_edge_parent()
932 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
945 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
956 	dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");  in msm_gpio_update_dual_edge_parent()
962 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_ack()  local
966 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {  in msm_gpio_irq_ack()
967 		if (test_bit(d->hwirq, pctrl->dual_edge_irqs))  in msm_gpio_irq_ack()
972 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_ack()
974 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_ack()
976 	msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_ack()
978 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))  in msm_gpio_irq_ack()
979 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_ack()
981 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_ack()
996 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_needs_dual_edge_parent_workaround()  local
999 	       pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&  in msm_gpio_needs_dual_edge_parent_workaround()
1000 	       test_bit(d->hwirq, pctrl->skip_wake_irqs);  in msm_gpio_needs_dual_edge_parent_workaround()
1006 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_set_type()  local
1013 		set_bit(d->hwirq, pctrl->dual_edge_irqs);  in msm_gpio_irq_set_type()
1022 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {  in msm_gpio_irq_set_type()
1023 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);  in msm_gpio_irq_set_type()
1028 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_set_type()
1030 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in msm_gpio_irq_set_type()
1036 		set_bit(d->hwirq, pctrl->dual_edge_irqs);  in msm_gpio_irq_set_type()
1038 		clear_bit(d->hwirq, pctrl->dual_edge_irqs);  in msm_gpio_irq_set_type()
1044 	if (pctrl->intr_target_use_scm) {  in msm_gpio_irq_set_type()
1045 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;  in msm_gpio_irq_set_type()
1055 			dev_err(pctrl->dev,  in msm_gpio_irq_set_type()
1059 		val = msm_readl_intr_target(pctrl, g);  in msm_gpio_irq_set_type()
1062 		msm_writel_intr_target(val, pctrl, g);  in msm_gpio_irq_set_type()
1070 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_set_type()
1119 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_set_type()
1127 		msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_set_type()
1129 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))  in msm_gpio_irq_set_type()
1130 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_set_type()
1132 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in msm_gpio_irq_set_type()
1145 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_set_wake()  local
1153 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_set_wake()
1156 	return irq_set_irq_wake(pctrl->irq, on);  in msm_gpio_irq_set_wake()
1162 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_reqres()  local
1168 	ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);  in msm_gpio_irq_reqres()
1206 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_set_affinity()  local
1208 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_set_affinity()
1217 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_set_vcpu_affinity()  local
1219 	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))  in msm_gpio_irq_set_vcpu_affinity()
1229 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_irq_handler()  local
1241 	for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {  in msm_gpio_irq_handler()
1242 		g = &pctrl->soc->groups[i];  in msm_gpio_irq_handler()
1243 		val = msm_readl_intr_status(pctrl, g);  in msm_gpio_irq_handler()
1263 	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);  in msm_gpio_wakeirq()  local
1270 	for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {  in msm_gpio_wakeirq()
1271 		map = &pctrl->soc->wakeirq_map[i];  in msm_gpio_wakeirq()
1281 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)  in msm_gpio_needs_valid_mask()  argument
1283 	if (pctrl->soc->reserved_gpios)  in msm_gpio_needs_valid_mask()
1286 	return device_property_count_u16(pctrl->dev, "gpios") > 0;  in msm_gpio_needs_valid_mask()
1309 static int msm_gpio_init(struct msm_pinctrl *pctrl)  in msm_gpio_init()  argument
1314 	unsigned gpio, ngpio = pctrl->soc->ngpios;  in msm_gpio_init()
1321 	chip = &pctrl->chip;  in msm_gpio_init()
1324 	chip->label = dev_name(pctrl->dev);  in msm_gpio_init()
1325 	chip->parent = pctrl->dev;  in msm_gpio_init()
1327 	if (msm_gpio_needs_valid_mask(pctrl))  in msm_gpio_init()
1330 	np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);  in msm_gpio_init()
1343 		for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {  in msm_gpio_init()
1344 			gpio = pctrl->soc->wakeirq_map[i].gpio;  in msm_gpio_init()
1345 			set_bit(gpio, pctrl->skip_wake_irqs);  in msm_gpio_init()
1352 	girq->fwnode = pctrl->dev->fwnode;  in msm_gpio_init()
1354 	girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),  in msm_gpio_init()
1360 	girq->parents[0] = pctrl->irq;  in msm_gpio_init()
1362 	ret = gpiochip_add_data(&pctrl->chip, pctrl);  in msm_gpio_init()
1364 		dev_err(pctrl->dev, "Failed register gpiochip\n");  in msm_gpio_init()
1378 	if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {  in msm_gpio_init()
1379 		ret = gpiochip_add_pin_range(&pctrl->chip,  in msm_gpio_init()
1380 			dev_name(pctrl->dev), 0, 0, chip->ngpio);  in msm_gpio_init()
1382 			dev_err(pctrl->dev, "Failed to add pin range\n");  in msm_gpio_init()
1383 			gpiochip_remove(&pctrl->chip);  in msm_gpio_init()
1394 	struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);  in msm_ps_hold_restart()  local
1396 	writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);  in msm_ps_hold_restart()
1408 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)  in msm_pinctrl_setup_pm_reset()  argument
1411 	const struct msm_function *func = pctrl->soc->functions;  in msm_pinctrl_setup_pm_reset()
1413 	for (i = 0; i < pctrl->soc->nfunctions; i++)  in msm_pinctrl_setup_pm_reset()
1415 			pctrl->restart_nb.notifier_call = msm_ps_hold_restart;  in msm_pinctrl_setup_pm_reset()
1416 			pctrl->restart_nb.priority = 128;  in msm_pinctrl_setup_pm_reset()
1417 			if (register_restart_handler(&pctrl->restart_nb))  in msm_pinctrl_setup_pm_reset()
1418 				dev_err(pctrl->dev,  in msm_pinctrl_setup_pm_reset()
1420 			poweroff_pctrl = pctrl;  in msm_pinctrl_setup_pm_reset()
1428 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);  in msm_pinctrl_suspend()  local
1430 	return pinctrl_force_sleep(pctrl->pctrl);  in msm_pinctrl_suspend()
1435 	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);  in msm_pinctrl_resume()  local
1437 	return pinctrl_force_default(pctrl->pctrl);  in msm_pinctrl_resume()
1448 	struct msm_pinctrl *pctrl;  in msm_pinctrl_probe()  local
1453 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);  in msm_pinctrl_probe()
1454 	if (!pctrl)  in msm_pinctrl_probe()
1457 	pctrl->dev = &pdev->dev;  in msm_pinctrl_probe()
1458 	pctrl->soc = soc_data;  in msm_pinctrl_probe()
1459 	pctrl->chip = msm_gpio_template;  in msm_pinctrl_probe()
1460 	pctrl->intr_target_use_scm = of_device_is_compatible(  in msm_pinctrl_probe()
1461 					pctrl->dev->of_node,  in msm_pinctrl_probe()
1464 	raw_spin_lock_init(&pctrl->lock);  in msm_pinctrl_probe()
1470 			pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);  in msm_pinctrl_probe()
1471 			if (IS_ERR(pctrl->regs[i]))  in msm_pinctrl_probe()
1472 				return PTR_ERR(pctrl->regs[i]);  in msm_pinctrl_probe()
1476 		pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);  in msm_pinctrl_probe()
1477 		if (IS_ERR(pctrl->regs[0]))  in msm_pinctrl_probe()
1478 			return PTR_ERR(pctrl->regs[0]);  in msm_pinctrl_probe()
1480 		pctrl->phys_base[0] = res->start;  in msm_pinctrl_probe()
1483 	msm_pinctrl_setup_pm_reset(pctrl);  in msm_pinctrl_probe()
1485 	pctrl->irq = platform_get_irq(pdev, 0);  in msm_pinctrl_probe()
1486 	if (pctrl->irq < 0)  in msm_pinctrl_probe()
1487 		return pctrl->irq;  in msm_pinctrl_probe()
1489 	pctrl->desc.owner = THIS_MODULE;  in msm_pinctrl_probe()
1490 	pctrl->desc.pctlops = &msm_pinctrl_ops;  in msm_pinctrl_probe()
1491 	pctrl->desc.pmxops = &msm_pinmux_ops;  in msm_pinctrl_probe()
1492 	pctrl->desc.confops = &msm_pinconf_ops;  in msm_pinctrl_probe()
1493 	pctrl->desc.name = dev_name(&pdev->dev);  in msm_pinctrl_probe()
1494 	pctrl->desc.pins = pctrl->soc->pins;  in msm_pinctrl_probe()
1495 	pctrl->desc.npins = pctrl->soc->npins;  in msm_pinctrl_probe()
1497 	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);  in msm_pinctrl_probe()
1498 	if (IS_ERR(pctrl->pctrl)) {  in msm_pinctrl_probe()
1500 		return PTR_ERR(pctrl->pctrl);  in msm_pinctrl_probe()
1503 	ret = msm_gpio_init(pctrl);  in msm_pinctrl_probe()
1507 	platform_set_drvdata(pdev, pctrl);  in msm_pinctrl_probe()
1517 	struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);  in msm_pinctrl_remove()  local
1519 	gpiochip_remove(&pctrl->chip);  in msm_pinctrl_remove()
1521 	unregister_restart_handler(&pctrl->restart_nb);  in msm_pinctrl_remove()