Lines Matching +full:edge +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/pinctrl/pinconf-generic.h>
31 #include "pinctrl-msm.h"
32 #include "../pinctrl-utils.h"
39 * struct msm_pinctrl - state for a pinctrl-msm device
50 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
113 return pctrl->soc->ngroups; in msm_get_groups_count()
121 return pctrl->soc->groups[group].name; in msm_get_group_name()
131 *pins = pctrl->soc->groups[group].pins; in msm_get_group_pins()
132 *num_pins = pctrl->soc->groups[group].npins; in msm_get_group_pins()
144 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) in msm_pinmux_request() argument
147 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
149 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; in msm_pinmux_request()
156 return pctrl->soc->nfunctions; in msm_get_functions_count()
164 return pctrl->soc->functions[function].name; in msm_get_function_name()
174 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
175 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
184 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
185 unsigned int irq = irq_find_mapping(gc->irq.domain, group); in msm_pinmux_set_mux()
187 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
188 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
194 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
195 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
197 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
198 if (g->funcs[i] == function) in msm_pinmux_set_mux()
202 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
203 return -EINVAL; in msm_pinmux_set_mux()
216 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
219 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
229 if (i == gpio_func && (val & BIT(g->oe_bit)) && in msm_pinmux_set_mux()
230 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
233 if (io_val & BIT(g->in_bit)) { in msm_pinmux_set_mux()
234 if (!(io_val & BIT(g->out_bit))) in msm_pinmux_set_mux()
235 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
237 if (io_val & BIT(g->out_bit)) in msm_pinmux_set_mux()
238 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
243 if (val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
244 val &= ~BIT(g->egpio_enable); in msm_pinmux_set_mux()
247 val |= i << g->mux_bit; in msm_pinmux_set_mux()
249 if (egpio_func && val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
250 val |= BIT(g->egpio_enable); in msm_pinmux_set_mux()
255 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
258 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
263 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
276 unsigned offset) in msm_pinmux_request_gpio() argument
279 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
282 if (!g->nfuncs) in msm_pinmux_request_gpio()
285 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
308 *bit = g->pull_bit; in msm_config_reg()
312 *bit = g->od_bit; in msm_config_reg()
316 *bit = g->drv_bit; in msm_config_reg()
321 *bit = g->oe_bit; in msm_config_reg()
325 return -ENOTSUPP; in msm_config_reg()
355 g = &pctrl->soc->groups[group]; in msm_config_group_get()
368 return -EINVAL; in msm_config_group_get()
373 return -EINVAL; in msm_config_group_get()
377 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
378 return -ENOTSUPP; in msm_config_group_get()
381 return -EINVAL; in msm_config_group_get()
385 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
390 return -EINVAL; in msm_config_group_get()
393 /* Pin is not open-drain */ in msm_config_group_get()
395 return -EINVAL; in msm_config_group_get()
404 return -EINVAL; in msm_config_group_get()
407 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
412 return -EINVAL; in msm_config_group_get()
416 return -ENOTSUPP; in msm_config_group_get()
440 g = &pctrl->soc->groups[group]; in msm_config_group_set()
459 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
460 return -ENOTSUPP; in msm_config_group_set()
465 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
476 arg = -1; in msm_config_group_set()
478 arg = (arg / 2) - 1; in msm_config_group_set()
482 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
485 val |= BIT(g->out_bit); in msm_config_group_set()
487 val &= ~BIT(g->out_bit); in msm_config_group_set()
489 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
499 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
501 return -EINVAL; in msm_config_group_set()
504 /* Range-check user-supplied value */ in msm_config_group_set()
506 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
507 return -EINVAL; in msm_config_group_set()
510 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
515 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
527 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in msm_gpio_direction_input() argument
534 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
536 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
539 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
542 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
547 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) in msm_gpio_direction_output() argument
554 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
556 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
560 val |= BIT(g->out_bit); in msm_gpio_direction_output()
562 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
566 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
569 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
574 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) in msm_gpio_get_direction() argument
580 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
584 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
588 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) in msm_gpio_get() argument
594 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
597 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
600 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in msm_gpio_set() argument
607 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
609 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
613 val |= BIT(g->out_bit); in msm_gpio_set()
615 val &= ~BIT(g->out_bit); in msm_gpio_set()
618 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
627 unsigned offset, in msm_gpio_dbg_show_one() argument
653 if (!gpiochip_line_is_valid(chip, offset)) in msm_gpio_dbg_show_one()
656 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
660 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
661 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
662 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
663 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
665 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
666 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); in msm_gpio_dbg_show_one()
669 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
671 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
674 seq_printf(s, " %-8s: egpio\n", g->name); in msm_gpio_dbg_show_one()
678 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
679 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); in msm_gpio_dbg_show_one()
681 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
690 unsigned gpio = chip->base; in msm_gpio_dbg_show()
693 for (i = 0; i < chip->ngpio; i++, gpio++) in msm_gpio_dbg_show()
708 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
716 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
717 return -EINVAL; in msm_gpio_init_valid_mask()
726 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
731 return -EINVAL; in msm_gpio_init_valid_mask()
735 return -ENOMEM; in msm_gpio_init_valid_mask()
737 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
739 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
763 /* For dual-edge interrupts in software, since some hardware has no
767 * settings of both-edge irq lines to try and catch the next edge.
770 * - the status bit goes high, indicating that an edge was caught, or
771 * - the input value of the gpio doesn't change during the attempt.
776 * The do-loop tries to sledge-hammer closed the timing hole between
777 * the initial value-read and the polarity-write - if the line value changes
792 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
795 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
798 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
802 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_pos()
803 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
815 if (d->parent_data) in msm_gpio_irq_mask()
818 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
821 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
823 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
828 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be in msm_gpio_irq_mask()
830 * an irq that it's configured for (either edge for edge type or level in msm_gpio_irq_mask()
831 * for level type irq). The 'non-raw' status enable bit causes the in msm_gpio_irq_mask()
833 * status bit is set. There's a bug though, the edge detection logic in msm_gpio_irq_mask()
835 * cause the status bit to latch spuriously when there isn't any edge in msm_gpio_irq_mask()
836 * so we can't touch that bit for edge type irqs and we have to keep in msm_gpio_irq_mask()
840 * enabled all the time causes level interrupts to re-latch into the in msm_gpio_irq_mask()
847 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
849 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
852 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
854 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
865 if (d->parent_data) in msm_gpio_irq_unmask()
868 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
871 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
873 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
876 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
877 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
880 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
882 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
890 gpiochip_enable_irq(gc, d->hwirq); in msm_gpio_irq_enable()
892 if (d->parent_data) in msm_gpio_irq_enable()
895 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
904 if (d->parent_data) in msm_gpio_irq_disable()
907 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
910 gpiochip_disable_irq(gc, d->hwirq); in msm_gpio_irq_disable()
914 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
926 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
931 /* Read the value and make a guess about what edge we need to catch */ in msm_gpio_update_dual_edge_parent()
932 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
936 /* Set the parent to catch the next edge */ in msm_gpio_update_dual_edge_parent()
941 * (and decided what edge we needed) and when set the edge. in msm_gpio_update_dual_edge_parent()
945 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
955 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_parent()
956 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
966 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
967 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
972 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
974 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
978 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
981 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
986 d = d->parent_data; in msm_gpio_irq_eoi()
989 d->chip->irq_eoi(d); in msm_gpio_irq_eoi()
999 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1000 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1013 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1019 if (d->parent_data) in msm_gpio_irq_set_type()
1022 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1023 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1028 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1030 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1035 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
1036 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1038 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1044 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1045 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1050 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
1051 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1055 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1057 d->hwirq); in msm_gpio_irq_set_type()
1060 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
1061 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1068 * could cause the INTR_STATUS to be set for EDGE interrupts. in msm_gpio_irq_set_type()
1071 was_enabled = val & BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1072 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1073 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1074 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1075 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1078 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1079 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1082 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1083 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1086 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1087 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1092 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1095 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1096 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1097 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1100 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1101 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1104 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1107 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1108 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1113 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1129 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1132 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1153 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1156 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1165 if (!try_module_get(gc->owner)) in msm_gpio_irq_reqres()
1166 return -ENODEV; in msm_gpio_irq_reqres()
1168 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1171 msm_gpio_direction_input(gc, d->hwirq); in msm_gpio_irq_reqres()
1173 if (gpiochip_lock_as_irq(gc, d->hwirq)) { in msm_gpio_irq_reqres()
1174 dev_err(gc->parent, in msm_gpio_irq_reqres()
1176 d->hwirq); in msm_gpio_irq_reqres()
1177 ret = -EINVAL; in msm_gpio_irq_reqres()
1182 * The disable / clear-enable workaround we do in msm_pinmux_set_mux() in msm_gpio_irq_reqres()
1186 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); in msm_gpio_irq_reqres()
1190 module_put(gc->owner); in msm_gpio_irq_reqres()
1198 gpiochip_unlock_as_irq(gc, d->hwirq); in msm_gpio_irq_relres()
1199 module_put(gc->owner); in msm_gpio_irq_relres()
1208 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1211 return -EINVAL; in msm_gpio_irq_set_affinity()
1219 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1222 return -EINVAL; in msm_gpio_irq_set_vcpu_affinity()
1241 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1242 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1244 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()
1245 generic_handle_domain_irq(gc->irq.domain, i); in msm_gpio_irq_handler()
1270 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1271 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1272 if (map->gpio == child) { in msm_gpio_wakeirq()
1273 *parent = map->wakeirq; in msm_gpio_wakeirq()
1283 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1286 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1314 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1319 return -EINVAL; in msm_gpio_init()
1321 chip = &pctrl->chip; in msm_gpio_init()
1322 chip->base = -1; in msm_gpio_init()
1323 chip->ngpio = ngpio; in msm_gpio_init()
1324 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1325 chip->parent = pctrl->dev; in msm_gpio_init()
1326 chip->owner = THIS_MODULE; in msm_gpio_init()
1328 chip->init_valid_mask = msm_gpio_init_valid_mask; in msm_gpio_init()
1330 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1332 chip->irq.parent_domain = irq_find_matching_host(np, in msm_gpio_init()
1335 if (!chip->irq.parent_domain) in msm_gpio_init()
1336 return -EPROBE_DEFER; in msm_gpio_init()
1337 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; in msm_gpio_init()
1342 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); in msm_gpio_init()
1343 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1344 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1345 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1349 girq = &chip->irq; in msm_gpio_init()
1351 girq->parent_handler = msm_gpio_irq_handler; in msm_gpio_init()
1352 girq->fwnode = pctrl->dev->fwnode; in msm_gpio_init()
1353 girq->num_parents = 1; in msm_gpio_init()
1354 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1356 if (!girq->parents) in msm_gpio_init()
1357 return -ENOMEM; in msm_gpio_init()
1358 girq->default_type = IRQ_TYPE_NONE; in msm_gpio_init()
1359 girq->handler = handle_bad_irq; in msm_gpio_init()
1360 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1362 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1364 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1369 * For DeviceTree-supported systems, the gpio core checks the in msm_gpio_init()
1370 * pinctrl's device node for the "gpio-ranges" property. in msm_gpio_init()
1375 * files which don't set the "gpio-ranges" property or systems that in msm_gpio_init()
1378 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1379 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1380 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1382 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1383 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1396 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1405 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); in msm_ps_hold_poweroff()
1411 const struct msm_function *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1413 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1415 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1416 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1417 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1418 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1430 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1437 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1453 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1455 return -ENOMEM; in msm_pinctrl_probe()
1457 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1458 pctrl->soc = soc_data; in msm_pinctrl_probe()
1459 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1460 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1461 pctrl->dev->of_node, in msm_pinctrl_probe()
1462 "qcom,ipq8064-pinctrl"); in msm_pinctrl_probe()
1464 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1466 if (soc_data->tiles) { in msm_pinctrl_probe()
1467 for (i = 0; i < soc_data->ntiles; i++) { in msm_pinctrl_probe()
1469 soc_data->tiles[i]); in msm_pinctrl_probe()
1470 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1471 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1472 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1476 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1477 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1478 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1480 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1485 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1486 if (pctrl->irq < 0) in msm_pinctrl_probe()
1487 return pctrl->irq; in msm_pinctrl_probe()
1489 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1490 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1491 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1492 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1493 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1494 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1495 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1497 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1498 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1499 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in msm_pinctrl_probe()
1500 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1509 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); in msm_pinctrl_probe()
1519 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1521 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()