Lines Matching +full:pctl +full:- +full:regmap
1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/regmap.h>
95 * (direction, retime-type, retime-clk, retime-delay)
97 * +----------------+
98 *[31:28]| reserved-3 |
99 * +----------------+-------------
101 * +----------------+ v
103 * +----------------+ ^
105 * +----------------+-------------
106 *[24] | reserved-2 |
107 * +----------------+-------------
109 * +----------------+ |
110 *[22] | retime-invclk | |
111 * +----------------+ v
112 *[21] |retime-clknotdat| [Retime-type ]
113 * +----------------+ ^
114 *[20] | retime-de | |
115 * +----------------+-------------
116 *[19:18]| retime-clk |------>[Retime-Clk ]
117 * +----------------+
118 *[17:16]| reserved-1 |
119 * +----------------+
120 *[15..0]| retime-delay |------>[Retime Delay]
121 * +----------------+
273 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
276 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
277 * --------------------------------------------------------
278 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
279 * --------------------------------------------------------
283 * ------- ----------------------------
284 * [0-3] - Description
285 * ------- ----------------------------
286 * 0000 - No edge IRQ.
287 * 0001 - Falling edge IRQ.
288 * 0010 - Rising edge IRQ.
289 * 0011 - Rising and Falling edge IRQ.
290 * ------- ----------------------------
322 struct pinctrl_dev *pctl; member
329 struct regmap *regmap; member
355 .oe = -1, /* Not Available */
356 .pu = -1, /* Not Available */
368 return &bank->pc; in st_get_pio_control()
385 struct regmap_field *output_enable = pc->oe; in st_pinconf_set_config()
386 struct regmap_field *pull_up = pc->pu; in st_pinconf_set_config()
387 struct regmap_field *open_drain = pc->od; in st_pinconf_set_config()
419 struct regmap_field *alt = pc->alt; in st_pctl_set_function()
435 struct regmap_field *alt = pc->alt; in st_pctl_get_pin_function()
451 int num_delay_times, i, closest_index = -1; in st_pinconf_delay_to_bit()
455 delay_times = data->output_delays; in st_pinconf_delay_to_bit()
456 num_delay_times = data->noutput_delays; in st_pinconf_delay_to_bit()
458 delay_times = data->input_delays; in st_pinconf_delay_to_bit()
459 num_delay_times = data->ninput_delays; in st_pinconf_delay_to_bit()
463 unsigned int divergence = abs(delay - delay_times[i]); in st_pinconf_delay_to_bit()
487 delay_times = data->output_delays; in st_pinconf_bit_to_delay()
488 num_delay_times = data->noutput_delays; in st_pinconf_bit_to_delay()
490 delay_times = data->input_delays; in st_pinconf_bit_to_delay()
491 num_delay_times = data->ninput_delays; in st_pinconf_bit_to_delay()
518 const struct st_pctl_data *data = info->data; in st_pinconf_set_retime_packed()
519 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_set_retime_packed()
522 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, in st_pinconf_set_retime_packed()
525 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, in st_pinconf_set_retime_packed()
528 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, in st_pinconf_set_retime_packed()
531 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, in st_pinconf_set_retime_packed()
534 st_regmap_field_bit_set_clear_pin(rt_p->retime, in st_pinconf_set_retime_packed()
540 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); in st_pinconf_set_retime_packed()
542 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); in st_pinconf_set_retime_packed()
557 info->data, config); in st_pinconf_set_retime_dedicated()
558 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_set_retime_dedicated()
569 regmap_field_write(rt_d->rt[pin], retime_config); in st_pinconf_set_retime_dedicated()
577 if (pc->oe) { in st_pinconf_get_direction()
578 regmap_field_read(pc->oe, &oe_value); in st_pinconf_get_direction()
583 if (pc->pu) { in st_pinconf_get_direction()
584 regmap_field_read(pc->pu, &pu_value); in st_pinconf_get_direction()
589 if (pc->od) { in st_pinconf_get_direction()
590 regmap_field_read(pc->od, &od_value); in st_pinconf_get_direction()
599 const struct st_pctl_data *data = info->data; in st_pinconf_get_retime_packed()
600 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pinconf_get_retime_packed()
604 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
607 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
610 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
613 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
616 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) in st_pinconf_get_retime_packed()
619 regmap_field_read(rt_p->delay_0, &delay0); in st_pinconf_get_retime_packed()
620 regmap_field_read(rt_p->delay_1, &delay1); in st_pinconf_get_retime_packed()
635 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pinconf_get_retime_dedicated()
637 regmap_field_read(rt_d->rt[pin], &value); in st_pinconf_get_retime_dedicated()
643 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); in st_pinconf_get_retime_dedicated()
667 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); in __st_gpio_set()
669 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); in __st_gpio_set()
686 * 0 0 0 [Input Weak pull-up] in st_gpio_direction()
696 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); in st_gpio_direction()
698 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); in st_gpio_direction()
706 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); in st_gpio_get()
717 pinctrl_gpio_direction_input(chip->base + offset); in st_gpio_direction_input()
728 pinctrl_gpio_direction_output(chip->base + offset); in st_gpio_direction_output()
736 struct st_pio_control pc = bank->pc; in st_gpio_get_direction()
755 * - See st_gpio_direction() above for an explanation in st_gpio_get_direction()
758 value = readl(bank->base + REG_PIO_PC(i)); in st_gpio_get_direction()
773 return info->ngroups; in st_pctl_get_groups_count()
781 return info->groups[selector].name; in st_pctl_get_group_name()
789 if (selector >= info->ngroups) in st_pctl_get_group_pins()
790 return -EINVAL; in st_pctl_get_group_pins()
792 *pins = info->groups[selector].pins; in st_pctl_get_group_pins()
793 *npins = info->groups[selector].npins; in st_pctl_get_group_pins()
803 for (i = 0; i < info->ngroups; i++) { in st_pctl_find_group_by_name()
804 if (!strcmp(info->groups[i].name, name)) in st_pctl_find_group_by_name()
805 return &info->groups[i]; in st_pctl_find_group_by_name()
816 struct device *dev = info->dev; in st_pctl_dt_node_to_map()
821 grp = st_pctl_find_group_by_name(info, np->name); in st_pctl_dt_node_to_map()
824 return -EINVAL; in st_pctl_dt_node_to_map()
827 map_num = grp->npins + 1; in st_pctl_dt_node_to_map()
830 return -ENOMEM; in st_pctl_dt_node_to_map()
835 return -EINVAL; in st_pctl_dt_node_to_map()
841 new_map[0].data.mux.function = parent->name; in st_pctl_dt_node_to_map()
842 new_map[0].data.mux.group = np->name; in st_pctl_dt_node_to_map()
847 for (i = 0; i < grp->npins; i++) { in st_pctl_dt_node_to_map()
850 pin_get_name(pctldev, grp->pins[i]); in st_pctl_dt_node_to_map()
851 new_map[i].data.configs.configs = &grp->pin_conf[i].config; in st_pctl_dt_node_to_map()
855 (*map)->data.mux.function, grp->name, map_num); in st_pctl_dt_node_to_map()
878 return info->nfunctions; in st_pmx_get_funcs_count()
886 return info->functions[selector].name; in st_pmx_get_fname()
893 *grps = info->functions[selector].groups; in st_pmx_get_groups()
894 *ngrps = info->functions[selector].ngroups; in st_pmx_get_groups()
903 struct st_pinconf *conf = info->groups[group].pin_conf; in st_pmx_set_mux()
907 for (i = 0; i < info->groups[group].npins; i++) { in st_pmx_set_mux()
925 st_pctl_set_function(&bank->pc, gpio, 0); in st_pmx_set_gpio_direction()
945 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_get_retime()
947 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_get_retime()
948 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_get_retime()
956 if (info->data->rt_style == st_retime_style_packed) in st_pinconf_set_retime()
958 else if (info->data->rt_style == st_retime_style_dedicated) in st_pinconf_set_retime()
959 if ((BIT(pin) & pc->rt_pin_mask)) in st_pinconf_set_retime()
1004 mutex_unlock(&pctldev->mutex); in st_pinconf_dbg_show()
1007 mutex_lock(&pctldev->mutex); in st_pinconf_dbg_show()
1015 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); in st_pinconf_dbg_show()
1018 "de:%ld,rt-clk:%ld,rt-delay:%ld]", in st_pinconf_dbg_show()
1042 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_dt_child_count()
1043 info->nbanks++; in st_pctl_dt_child_count()
1045 info->nfunctions++; in st_pctl_dt_child_count()
1046 info->ngroups += of_get_child_count(child); in st_pctl_dt_child_count()
1054 struct device *dev = info->dev; in st_pctl_dt_setup_retime_packed()
1055 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_packed()
1056 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_packed()
1058 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_packed()
1059 struct st_retime_packed *rt_p = &pc->rt.rt_p; in st_pctl_dt_setup_retime_packed()
1070 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); in st_pctl_dt_setup_retime_packed()
1071 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); in st_pctl_dt_setup_retime_packed()
1072 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); in st_pctl_dt_setup_retime_packed()
1073 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); in st_pctl_dt_setup_retime_packed()
1074 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); in st_pctl_dt_setup_retime_packed()
1075 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); in st_pctl_dt_setup_retime_packed()
1076 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); in st_pctl_dt_setup_retime_packed()
1078 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || in st_pctl_dt_setup_retime_packed()
1079 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || in st_pctl_dt_setup_retime_packed()
1080 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || in st_pctl_dt_setup_retime_packed()
1081 IS_ERR(rt_p->double_edge)) in st_pctl_dt_setup_retime_packed()
1082 return -EINVAL; in st_pctl_dt_setup_retime_packed()
1090 struct device *dev = info->dev; in st_pctl_dt_setup_retime_dedicated()
1091 struct regmap *rm = info->regmap; in st_pctl_dt_setup_retime_dedicated()
1092 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime_dedicated()
1094 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_dedicated()
1095 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; in st_pctl_dt_setup_retime_dedicated()
1097 u32 pin_mask = pc->rt_pin_mask; in st_pctl_dt_setup_retime_dedicated()
1102 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); in st_pctl_dt_setup_retime_dedicated()
1103 if (IS_ERR(rt_d->rt[j])) in st_pctl_dt_setup_retime_dedicated()
1104 return -EINVAL; in st_pctl_dt_setup_retime_dedicated()
1114 const struct st_pctl_data *data = info->data; in st_pctl_dt_setup_retime()
1115 if (data->rt_style == st_retime_style_packed) in st_pctl_dt_setup_retime()
1117 else if (data->rt_style == st_retime_style_dedicated) in st_pctl_dt_setup_retime()
1120 return -EINVAL; in st_pctl_dt_setup_retime()
1125 struct regmap *regmap, int bank, in st_pc_get_value() argument
1133 return devm_regmap_field_alloc(dev, regmap, reg); in st_pc_get_value()
1139 const struct st_pctl_data *data = info->data; in st_parse_syscfgs()
1146 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; in st_parse_syscfgs()
1147 struct st_pio_control *pc = &info->banks[bank].pc; in st_parse_syscfgs()
1148 struct device *dev = info->dev; in st_parse_syscfgs()
1149 struct regmap *regmap = info->regmap; in st_parse_syscfgs() local
1151 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); in st_parse_syscfgs()
1152 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); in st_parse_syscfgs()
1153 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); in st_parse_syscfgs()
1154 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); in st_parse_syscfgs()
1157 pc->rt_pin_mask = 0xff; in st_parse_syscfgs()
1158 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); in st_parse_syscfgs()
1169 int retval = -EINVAL; in st_pctl_dt_calculate_pin()
1174 return -EINVAL; in st_pctl_dt_calculate_pin()
1176 for (i = 0; i < info->nbanks; i++) { in st_pctl_dt_calculate_pin()
1177 chip = &info->banks[i].gpio_chip; in st_pctl_dt_calculate_pin()
1178 if (chip->of_node == np) { in st_pctl_dt_calculate_pin()
1179 if (offset < chip->ngpio) in st_pctl_dt_calculate_pin()
1180 retval = chip->base + offset; in st_pctl_dt_calculate_pin()
1199 struct device *dev = info->dev; in st_pctl_dt_parse_groups()
1208 return -ENODATA; in st_pctl_dt_parse_groups()
1212 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1215 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { in st_pctl_dt_parse_groups()
1219 ret = -EINVAL; in st_pctl_dt_parse_groups()
1224 grp->npins = npins; in st_pctl_dt_parse_groups()
1225 grp->name = np->name; in st_pctl_dt_parse_groups()
1226 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); in st_pctl_dt_parse_groups()
1227 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); in st_pctl_dt_parse_groups()
1229 if (!grp->pins || !grp->pin_conf) { in st_pctl_dt_parse_groups()
1230 ret = -ENOMEM; in st_pctl_dt_parse_groups()
1236 if (!strcmp(pp->name, "name")) in st_pctl_dt_parse_groups()
1238 nr_props = pp->length/sizeof(u32); in st_pctl_dt_parse_groups()
1239 list = pp->value; in st_pctl_dt_parse_groups()
1240 conf = &grp->pin_conf[i]; in st_pctl_dt_parse_groups()
1245 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset); in st_pctl_dt_parse_groups()
1246 conf->name = pp->name; in st_pctl_dt_parse_groups()
1247 grp->pins[i] = conf->pin; in st_pctl_dt_parse_groups()
1249 conf->altfunc = be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1250 conf->config = 0; in st_pctl_dt_parse_groups()
1252 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1256 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1258 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1261 conf->config |= be32_to_cpup(list++); in st_pctl_dt_parse_groups()
1275 struct device *dev = info->dev; in st_pctl_parse_functions()
1281 func = &info->functions[index]; in st_pctl_parse_functions()
1282 func->name = np->name; in st_pctl_parse_functions()
1283 func->ngroups = of_get_child_count(np); in st_pctl_parse_functions()
1284 if (func->ngroups == 0) in st_pctl_parse_functions()
1285 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); in st_pctl_parse_functions()
1286 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); in st_pctl_parse_functions()
1287 if (!func->groups) in st_pctl_parse_functions()
1288 return -ENOMEM; in st_pctl_parse_functions()
1292 func->groups[i] = child->name; in st_pctl_parse_functions()
1293 grp = &info->groups[*grp_index]; in st_pctl_parse_functions()
1301 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); in st_pctl_parse_functions()
1311 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); in st_gpio_irq_mask()
1319 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); in st_gpio_irq_unmask()
1326 st_gpio_direction_input(gc, d->hwirq); in st_gpio_irq_request_resources()
1328 return gpiochip_lock_as_irq(gc, d->hwirq); in st_gpio_irq_request_resources()
1335 gpiochip_unlock_as_irq(gc, d->hwirq); in st_gpio_irq_release_resources()
1343 int comp, pin = d->hwirq; in st_gpio_irq_set_type()
1363 comp = st_gpio_get(&bank->gpio_chip, pin); in st_gpio_irq_set_type()
1367 return -EINVAL; in st_gpio_irq_set_type()
1370 spin_lock_irqsave(&bank->lock, flags); in st_gpio_irq_set_type()
1371 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( in st_gpio_irq_set_type()
1373 bank->irq_edge_conf |= pin_edge_conf; in st_gpio_irq_set_type()
1374 spin_unlock_irqrestore(&bank->lock, flags); in st_gpio_irq_set_type()
1376 val = readl(bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1379 writel(val, bank->base + REG_PIO_PCOMP); in st_gpio_irq_set_type()
1396 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1400 * step-1 ________ __________
1401 * | | step - 3
1403 * step -2 |_____|
1414 spin_lock_irqsave(&bank->lock, flags); in __gpio_irq_handler()
1415 bank_edge_mask = bank->irq_edge_conf; in __gpio_irq_handler()
1416 spin_unlock_irqrestore(&bank->lock, flags); in __gpio_irq_handler()
1419 port_in = readl(bank->base + REG_PIO_PIN); in __gpio_irq_handler()
1420 port_comp = readl(bank->base + REG_PIO_PCOMP); in __gpio_irq_handler()
1421 port_mask = readl(bank->base + REG_PIO_PMASK); in __gpio_irq_handler()
1434 val = st_gpio_get(&bank->gpio_chip, n); in __gpio_irq_handler()
1437 val ? bank->base + REG_PIO_SET_PCOMP : in __gpio_irq_handler()
1438 bank->base + REG_PIO_CLR_PCOMP); in __gpio_irq_handler()
1445 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); in __gpio_irq_handler()
1471 status = readl(info->irqmux_base); in st_gpio_irqmux_handler()
1473 for_each_set_bit(n, &status, info->nbanks) in st_gpio_irqmux_handler()
1474 __gpio_irq_handler(&info->banks[n]); in st_gpio_irqmux_handler()
1504 struct st_gpio_bank *bank = &info->banks[bank_nr]; in st_gpiolib_register_bank()
1505 struct pinctrl_gpio_range *range = &bank->range; in st_gpiolib_register_bank()
1506 struct device *dev = info->dev; in st_gpiolib_register_bank()
1512 return -ENODEV; in st_gpiolib_register_bank()
1514 bank->base = devm_ioremap_resource(dev, &res); in st_gpiolib_register_bank()
1515 if (IS_ERR(bank->base)) in st_gpiolib_register_bank()
1516 return PTR_ERR(bank->base); in st_gpiolib_register_bank()
1518 bank->gpio_chip = st_gpio_template; in st_gpiolib_register_bank()
1519 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1520 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1521 bank->gpio_chip.of_node = np; in st_gpiolib_register_bank()
1522 bank->gpio_chip.parent = dev; in st_gpiolib_register_bank()
1523 spin_lock_init(&bank->lock); in st_gpiolib_register_bank()
1525 of_property_read_string(np, "st,bank-name", &range->name); in st_gpiolib_register_bank()
1526 bank->gpio_chip.label = range->name; in st_gpiolib_register_bank()
1528 range->id = bank_num; in st_gpiolib_register_bank()
1529 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; in st_gpiolib_register_bank()
1530 range->npins = bank->gpio_chip.ngpio; in st_gpiolib_register_bank()
1531 range->gc = &bank->gpio_chip; in st_gpiolib_register_bank()
1535 * interrupt-wirings. in st_gpiolib_register_bank()
1541 * | |----> [gpio-bank (n) ] in st_gpiolib_register_bank()
1542 * | |----> [gpio-bank (n + 1)] in st_gpiolib_register_bank()
1543 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] in st_gpiolib_register_bank()
1544 * | |----> [gpio-bank (... )] in st_gpiolib_register_bank()
1545 * |_________|----> [gpio-bank (n + 7)] in st_gpiolib_register_bank()
1549 * [irqN]----> [gpio-bank (n)] in st_gpiolib_register_bank()
1562 if (!info->irqmux_base) { in st_gpiolib_register_bank()
1567 girq = &bank->gpio_chip.irq; in st_gpiolib_register_bank()
1568 girq->chip = &st_gpio_irqchip; in st_gpiolib_register_bank()
1569 girq->parent_handler = st_gpio_irq_handler; in st_gpiolib_register_bank()
1570 girq->num_parents = 1; in st_gpiolib_register_bank()
1571 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), in st_gpiolib_register_bank()
1573 if (!girq->parents) in st_gpiolib_register_bank()
1574 return -ENOMEM; in st_gpiolib_register_bank()
1575 girq->parents[0] = gpio_irq; in st_gpiolib_register_bank()
1576 girq->default_type = IRQ_TYPE_NONE; in st_gpiolib_register_bank()
1577 girq->handler = handle_simple_irq; in st_gpiolib_register_bank()
1581 err = gpiochip_add_data(&bank->gpio_chip, bank); in st_gpiolib_register_bank()
1584 dev_info(dev, "%s bank added.\n", range->name); in st_gpiolib_register_bank()
1590 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1591 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1592 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1593 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1600 struct device *dev = &pdev->dev; in st_pctl_probe_dt()
1604 struct device_node *np = dev->of_node; in st_pctl_probe_dt()
1610 if (!info->nbanks) in st_pctl_probe_dt()
1611 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); in st_pctl_probe_dt()
1613 dev_info(dev, "nbanks = %d\n", info->nbanks); in st_pctl_probe_dt()
1614 dev_info(dev, "nfunctions = %d\n", info->nfunctions); in st_pctl_probe_dt()
1615 dev_info(dev, "ngroups = %d\n", info->ngroups); in st_pctl_probe_dt()
1617 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); in st_pctl_probe_dt()
1619 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); in st_pctl_probe_dt()
1621 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); in st_pctl_probe_dt()
1623 if (!info->functions || !info->groups || !info->banks) in st_pctl_probe_dt()
1624 return -ENOMEM; in st_pctl_probe_dt()
1626 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in st_pctl_probe_dt()
1627 if (IS_ERR(info->regmap)) in st_pctl_probe_dt()
1628 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); in st_pctl_probe_dt()
1629 info->data = of_match_node(st_pctl_of_match, np)->data; in st_pctl_probe_dt()
1634 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); in st_pctl_probe_dt()
1635 if (IS_ERR(info->irqmux_base)) in st_pctl_probe_dt()
1636 return PTR_ERR(info->irqmux_base); in st_pctl_probe_dt()
1642 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; in st_pctl_probe_dt()
1643 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); in st_pctl_probe_dt()
1645 return -ENOMEM; in st_pctl_probe_dt()
1647 pctl_desc->pins = pdesc; in st_pctl_probe_dt()
1651 if (of_property_read_bool(child, "gpio-controller")) { in st_pctl_probe_dt()
1661 k = info->banks[bank].range.pin_base; in st_pctl_probe_dt()
1662 bank_name = info->banks[bank].range.name; in st_pctl_probe_dt()
1671 pdesc->number = k; in st_pctl_probe_dt()
1672 pdesc->name = pin_names[j]; in st_pctl_probe_dt()
1693 struct device *dev = &pdev->dev; in st_pctl_probe()
1698 if (!dev->of_node) { in st_pctl_probe()
1700 return -EINVAL; in st_pctl_probe()
1705 return -ENOMEM; in st_pctl_probe()
1709 return -ENOMEM; in st_pctl_probe()
1711 info->dev = dev; in st_pctl_probe()
1717 pctl_desc->owner = THIS_MODULE; in st_pctl_probe()
1718 pctl_desc->pctlops = &st_pctlops; in st_pctl_probe()
1719 pctl_desc->pmxops = &st_pmxops; in st_pctl_probe()
1720 pctl_desc->confops = &st_confops; in st_pctl_probe()
1721 pctl_desc->name = dev_name(dev); in st_pctl_probe()
1723 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); in st_pctl_probe()
1724 if (IS_ERR(info->pctl)) in st_pctl_probe()
1725 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); in st_pctl_probe()
1727 for (i = 0; i < info->nbanks; i++) in st_pctl_probe()
1728 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); in st_pctl_probe()
1735 .name = "st-pinctrl",