Lines Matching +full:pctl +full:- +full:regmap
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
81 * struct pcs_function - pinctrl function
103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
117 * struct pcs_data - wrapper for data needed by pinctrl framework
131 * struct pcs_soc_data - SoC specific settings
136 * @rearm: optional SoC specific wake-up rearm function
147 * struct pcs_device - pinctrl device instance
154 * @pctl: pin controller device
183 struct pinctrl_dev *pctl; member
210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
235 * REVISIT: Reads and writes could eventually use regmap or something
239 * write like regmap is doing is not desired, and caching the registers
276 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
278 if (pcs->bits_per_mux) { in pcs_pin_reg_offset_get()
281 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
291 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; in pcs_pin_shift_reg_get()
306 val = pcs->read(pcs->base + offset); in pcs_pin_dbg_show()
308 if (pcs->bits_per_mux) in pcs_pin_dbg_show()
309 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin); in pcs_pin_dbg_show()
311 pa = pcs->res->start + offset; in pcs_pin_dbg_show()
322 devm_kfree(pcs->dev, map); in pcs_dt_free_map()
348 setting = pdesc->mux_setting; in pcs_get_function()
350 return -ENOTSUPP; in pcs_get_function()
351 fselector = setting->func; in pcs_get_function()
353 *func = function->data; in pcs_get_function()
355 dev_err(pcs->dev, "%s could not find function%i\n", in pcs_get_function()
357 return -ENOTSUPP; in pcs_get_function()
372 if (!pcs->fmask) in pcs_set_mux()
375 func = function->data; in pcs_set_mux()
377 return -EINVAL; in pcs_set_mux()
379 dev_dbg(pcs->dev, "enabling %s function%i\n", in pcs_set_mux()
380 func->name, fselector); in pcs_set_mux()
382 for (i = 0; i < func->nvals; i++) { in pcs_set_mux()
387 vals = &func->vals[i]; in pcs_set_mux()
388 raw_spin_lock_irqsave(&pcs->lock, flags); in pcs_set_mux()
389 val = pcs->read(vals->reg); in pcs_set_mux()
391 if (pcs->bits_per_mux) in pcs_set_mux()
392 mask = vals->mask; in pcs_set_mux()
394 mask = pcs->fmask; in pcs_set_mux()
397 val |= (vals->val & mask); in pcs_set_mux()
398 pcs->write(val, vals->reg); in pcs_set_mux()
399 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pcs_set_mux()
414 if (!pcs->fmask) in pcs_request_gpio()
415 return -ENOTSUPP; in pcs_request_gpio()
417 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { in pcs_request_gpio()
421 if (pin >= frange->offset + frange->npins in pcs_request_gpio()
422 || pin < frange->offset) in pcs_request_gpio()
427 if (pcs->bits_per_mux) { in pcs_request_gpio()
430 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
431 data &= ~(pcs->fmask << pin_shift); in pcs_request_gpio()
432 data |= frange->gpiofunc << pin_shift; in pcs_request_gpio()
433 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
435 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
436 data &= ~pcs->fmask; in pcs_request_gpio()
437 data |= frange->gpiofunc; in pcs_request_gpio()
438 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
495 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_get()
502 return -ENOTSUPP; in pcs_pinconf_get()
504 } else if (param != func->conf[i].param) { in pcs_pinconf_get()
508 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_get()
509 data = pcs->read(pcs->base + offset) & func->conf[i].mask; in pcs_pinconf_get()
510 switch (func->conf[i].param) { in pcs_pinconf_get()
515 if ((data != func->conf[i].enable) || in pcs_pinconf_get()
516 (data == func->conf[i].disable)) in pcs_pinconf_get()
517 return -ENOTSUPP; in pcs_pinconf_get()
522 for (j = 0; j < func->nconfs; j++) { in pcs_pinconf_get()
523 switch (func->conf[j].param) { in pcs_pinconf_get()
525 if (data != func->conf[j].enable) in pcs_pinconf_get()
526 return -ENOTSUPP; in pcs_pinconf_get()
544 return -ENOTSUPP; in pcs_pinconf_get()
562 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_set()
564 != func->conf[i].param) in pcs_pinconf_set()
567 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_set()
568 data = pcs->read(pcs->base + offset); in pcs_pinconf_set()
570 switch (func->conf[i].param) { in pcs_pinconf_set()
577 shift = ffs(func->conf[i].mask) - 1; in pcs_pinconf_set()
578 data &= ~func->conf[i].mask; in pcs_pinconf_set()
579 data |= (arg << shift) & func->conf[i].mask; in pcs_pinconf_set()
591 data &= ~func->conf[i].mask; in pcs_pinconf_set()
593 data |= func->conf[i].enable; in pcs_pinconf_set()
595 data |= func->conf[i].disable; in pcs_pinconf_set()
598 return -ENOTSUPP; in pcs_pinconf_set()
600 pcs->write(data, pcs->base + offset); in pcs_pinconf_set()
604 if (i >= func->nconfs) in pcs_pinconf_set()
605 return -ENOTSUPP; in pcs_pinconf_set()
623 return -ENOTSUPP; in pcs_pinconf_group_get()
626 return -ENOTSUPP; in pcs_pinconf_group_get()
645 return -ENOTSUPP; in pcs_pinconf_group_set()
679 * pcs_add_pin() - add a pin to the static per controller pin array
685 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_add_pin()
689 i = pcs->pins.cur; in pcs_add_pin()
690 if (i >= pcs->desc.npins) { in pcs_add_pin()
691 dev_err(pcs->dev, "too many pins, max %i\n", in pcs_add_pin()
692 pcs->desc.npins); in pcs_add_pin()
693 return -ENOMEM; in pcs_add_pin()
696 if (pcs_soc->irq_enable_mask) { in pcs_add_pin()
699 val = pcs->read(pcs->base + offset); in pcs_add_pin()
700 if (val & pcs_soc->irq_enable_mask) { in pcs_add_pin()
701 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", in pcs_add_pin()
702 (unsigned long)pcs->res->start + offset, val); in pcs_add_pin()
703 val &= ~pcs_soc->irq_enable_mask; in pcs_add_pin()
704 pcs->write(val, pcs->base + offset); in pcs_add_pin()
708 pin = &pcs->pins.pa[i]; in pcs_add_pin()
709 pin->number = i; in pcs_add_pin()
710 pcs->pins.cur++; in pcs_add_pin()
716 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
728 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_allocate_pin_table()
730 if (pcs->bits_per_mux && pcs->fmask) { in pcs_allocate_pin_table()
731 pcs->bits_per_pin = fls(pcs->fmask); in pcs_allocate_pin_table()
732 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_allocate_pin_table()
734 nr_pins = pcs->size / mux_bytes; in pcs_allocate_pin_table()
737 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); in pcs_allocate_pin_table()
738 pcs->pins.pa = devm_kcalloc(pcs->dev, in pcs_allocate_pin_table()
739 nr_pins, sizeof(*pcs->pins.pa), in pcs_allocate_pin_table()
741 if (!pcs->pins.pa) in pcs_allocate_pin_table()
742 return -ENOMEM; in pcs_allocate_pin_table()
744 pcs->desc.pins = pcs->pins.pa; in pcs_allocate_pin_table()
745 pcs->desc.npins = nr_pins; in pcs_allocate_pin_table()
747 for (i = 0; i < pcs->desc.npins; i++) { in pcs_allocate_pin_table()
754 dev_err(pcs->dev, "error adding pins: %i\n", res); in pcs_allocate_pin_table()
763 * pcs_add_function() - adds a new function to the function list
785 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); in pcs_add_function()
787 return -ENOMEM; in pcs_add_function()
789 function->vals = vals; in pcs_add_function()
790 function->nvals = nvals; in pcs_add_function()
791 function->name = name; in pcs_add_function()
793 selector = pinmux_generic_add_function(pcs->pctl, name, in pcs_add_function()
797 devm_kfree(pcs->dev, function); in pcs_add_function()
807 * pcs_get_pin_by_offset() - get a pin index based on the register offset
817 if (offset >= pcs->size) { in pcs_get_pin_by_offset()
818 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", in pcs_get_pin_by_offset()
819 offset, pcs->size); in pcs_get_pin_by_offset()
820 return -EINVAL; in pcs_get_pin_by_offset()
823 if (pcs->bits_per_mux) in pcs_get_pin_by_offset()
824 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_get_pin_by_offset()
826 index = offset / (pcs->width / BITS_PER_BYTE); in pcs_get_pin_by_offset()
838 int ret = -EINVAL; in pcs_config_match()
851 (*conf)->param = param; in add_config()
852 (*conf)->val = value; in add_config()
853 (*conf)->enable = enable; in add_config()
854 (*conf)->disable = disable; in add_config()
855 (*conf)->mask = mask; in add_config()
879 shift = ffs(value[1]) - 1; in pcs_add_conf2()
898 dev_err(pcs->dev, "mask field of the property can't be 0\n"); in pcs_add_conf4()
906 dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); in pcs_add_conf4()
921 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, in pcs_parse_pinconf()
922 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, in pcs_parse_pinconf()
923 { "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, }, in pcs_parse_pinconf()
924 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, in pcs_parse_pinconf()
925 { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, }, in pcs_parse_pinconf()
928 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, in pcs_parse_pinconf()
929 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, in pcs_parse_pinconf()
930 { "pinctrl-single,input-schmitt-enable", in pcs_parse_pinconf()
936 return -ENOTSUPP; in pcs_parse_pinconf()
948 return -ENOTSUPP; in pcs_parse_pinconf()
950 func->conf = devm_kcalloc(pcs->dev, in pcs_parse_pinconf()
953 if (!func->conf) in pcs_parse_pinconf()
954 return -ENOMEM; in pcs_parse_pinconf()
955 func->nconfs = nconfs; in pcs_parse_pinconf()
956 conf = &(func->conf[0]); in pcs_parse_pinconf()
958 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long), in pcs_parse_pinconf()
961 return -ENOMEM; in pcs_parse_pinconf()
970 m->type = PIN_MAP_TYPE_CONFIGS_GROUP; in pcs_parse_pinconf()
971 m->data.configs.group_or_pin = np->name; in pcs_parse_pinconf()
972 m->data.configs.configs = settings; in pcs_parse_pinconf()
973 m->data.configs.num_configs = nconfs; in pcs_parse_pinconf()
978 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
1002 const char *name = "pinctrl-single,pins"; in pcs_parse_one_pinctrl_entry()
1004 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; in pcs_parse_one_pinctrl_entry()
1009 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_one_pinctrl_entry()
1010 return -EINVAL; in pcs_parse_one_pinctrl_entry()
1013 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1015 return -ENOMEM; in pcs_parse_one_pinctrl_entry()
1017 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1031 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_one_pinctrl_entry()
1037 vals[found].reg = pcs->base + offset; in pcs_parse_one_pinctrl_entry()
1048 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n", in pcs_parse_one_pinctrl_entry()
1053 dev_err(pcs->dev, in pcs_parse_one_pinctrl_entry()
1061 pgnames[0] = np->name; in pcs_parse_one_pinctrl_entry()
1062 mutex_lock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1063 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_one_pinctrl_entry()
1070 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_one_pinctrl_entry()
1076 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_one_pinctrl_entry()
1077 (*map)->data.mux.group = np->name; in pcs_parse_one_pinctrl_entry()
1078 (*map)->data.mux.function = np->name; in pcs_parse_one_pinctrl_entry()
1084 else if (res == -ENOTSUPP) in pcs_parse_one_pinctrl_entry()
1091 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1096 pinctrl_generic_remove_group(pcs->pctl, gsel); in pcs_parse_one_pinctrl_entry()
1099 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_one_pinctrl_entry()
1101 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1102 devm_kfree(pcs->dev, pins); in pcs_parse_one_pinctrl_entry()
1105 devm_kfree(pcs->dev, vals); in pcs_parse_one_pinctrl_entry()
1116 const char *name = "pinctrl-single,bits"; in pcs_parse_bits_in_pinctrl_entry()
1118 int rows, *pins, found = 0, res = -ENOMEM, i, fsel; in pcs_parse_bits_in_pinctrl_entry()
1124 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_bits_in_pinctrl_entry()
1125 return -EINVAL; in pcs_parse_bits_in_pinctrl_entry()
1129 dev_err(pcs->dev, "pinconf not supported\n"); in pcs_parse_bits_in_pinctrl_entry()
1130 return -ENOTSUPP; in pcs_parse_bits_in_pinctrl_entry()
1133 npins_in_row = pcs->width / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1135 vals = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1139 return -ENOMEM; in pcs_parse_bits_in_pinctrl_entry()
1141 pins = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1159 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_bits_in_pinctrl_entry()
1169 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n", in pcs_parse_bits_in_pinctrl_entry()
1175 pin_num_from_lsb = bit_pos / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1176 mask_pos = ((pcs->fmask) << bit_pos); in pcs_parse_bits_in_pinctrl_entry()
1181 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1190 dev_warn(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1197 vals[found].reg = pcs->base + offset; in pcs_parse_bits_in_pinctrl_entry()
1202 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1211 pgnames[0] = np->name; in pcs_parse_bits_in_pinctrl_entry()
1212 mutex_lock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1213 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_bits_in_pinctrl_entry()
1220 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_bits_in_pinctrl_entry()
1224 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_bits_in_pinctrl_entry()
1225 (*map)->data.mux.group = np->name; in pcs_parse_bits_in_pinctrl_entry()
1226 (*map)->data.mux.function = np->name; in pcs_parse_bits_in_pinctrl_entry()
1229 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1234 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_bits_in_pinctrl_entry()
1236 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1237 devm_kfree(pcs->dev, pins); in pcs_parse_bits_in_pinctrl_entry()
1240 devm_kfree(pcs->dev, vals); in pcs_parse_bits_in_pinctrl_entry()
1245 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1262 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL); in pcs_dt_node_to_map()
1264 return -ENOMEM; in pcs_dt_node_to_map()
1268 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); in pcs_dt_node_to_map()
1270 ret = -ENOMEM; in pcs_dt_node_to_map()
1274 if (pcs->bits_per_mux) { in pcs_dt_node_to_map()
1278 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1286 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1295 devm_kfree(pcs->dev, pgnames); in pcs_dt_node_to_map()
1297 devm_kfree(pcs->dev, *map); in pcs_dt_node_to_map()
1303 * pcs_irq_free() - free interrupt
1308 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_free()
1310 if (pcs_soc->irq < 0) in pcs_irq_free()
1313 if (pcs->domain) in pcs_irq_free()
1314 irq_domain_remove(pcs->domain); in pcs_irq_free()
1317 free_irq(pcs_soc->irq, pcs_soc); in pcs_irq_free()
1319 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_free()
1323 * pcs_free_resources() - free memory used by this driver
1329 pinctrl_unregister(pcs->pctl); in pcs_free_resources()
1332 if (pcs->missing_nr_pinctrl_cells) in pcs_free_resources()
1333 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); in pcs_free_resources()
1339 const char *propname = "pinctrl-single,gpio-range"; in pcs_add_gpio_func()
1340 const char *cellname = "#pinctrl-single,gpio-range-cells"; in pcs_add_gpio_func()
1353 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); in pcs_add_gpio_func()
1355 ret = -ENOMEM; in pcs_add_gpio_func()
1358 range->offset = gpiospec.args[0]; in pcs_add_gpio_func()
1359 range->npins = gpiospec.args[1]; in pcs_add_gpio_func()
1360 range->gpiofunc = gpiospec.args[2]; in pcs_add_gpio_func()
1361 mutex_lock(&pcs->mutex); in pcs_add_gpio_func()
1362 list_add_tail(&range->node, &pcs->gpiofuncs); in pcs_add_gpio_func()
1363 mutex_unlock(&pcs->mutex); in pcs_add_gpio_func()
1383 * pcs_irq_set() - enables or disables an interrupt
1389 * register that is typically used for wake-up events.
1399 list_for_each(pos, &pcs->irqs) { in pcs_irq_set()
1404 if (irq != pcswi->irq) in pcs_irq_set()
1407 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1408 raw_spin_lock(&pcs->lock); in pcs_irq_set()
1409 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1414 pcs->write(mask, pcswi->reg); in pcs_irq_set()
1417 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1418 raw_spin_unlock(&pcs->lock); in pcs_irq_set()
1421 if (pcs_soc->rearm) in pcs_irq_set()
1422 pcs_soc->rearm(); in pcs_irq_set()
1426 * pcs_irq_mask() - mask pinctrl interrupt
1433 pcs_irq_set(pcs_soc, d->irq, false); in pcs_irq_mask()
1437 * pcs_irq_unmask() - unmask pinctrl interrupt
1444 pcs_irq_set(pcs_soc, d->irq, true); in pcs_irq_unmask()
1448 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1450 * @state: wake-up state
1453 * For runtime PM, the wake-up events should be enabled by default.
1466 * pcs_irq_handle() - common interrupt handler
1470 * mux register. This interrupt is typically used for wake-up events.
1480 list_for_each(pos, &pcs->irqs) { in pcs_irq_handle()
1485 raw_spin_lock(&pcs->lock); in pcs_irq_handle()
1486 mask = pcs->read(pcswi->reg); in pcs_irq_handle()
1487 raw_spin_unlock(&pcs->lock); in pcs_irq_handle()
1488 if (mask & pcs_soc->irq_status_mask) { in pcs_irq_handle()
1489 generic_handle_domain_irq(pcs->domain, in pcs_irq_handle()
1490 pcswi->hwirq); in pcs_irq_handle()
1499 * pcs_irq_handler() - handler for the shared interrupt case
1504 * pinctrl-single share a single interrupt like on omaps.
1514 * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case
1518 * pinctrl-single instance.
1535 struct pcs_soc_data *pcs_soc = d->host_data; in pcs_irqdomain_map()
1540 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); in pcs_irqdomain_map()
1542 return -ENOMEM; in pcs_irqdomain_map()
1544 pcswi->reg = pcs->base + hwirq; in pcs_irqdomain_map()
1545 pcswi->hwirq = hwirq; in pcs_irqdomain_map()
1546 pcswi->irq = irq; in pcs_irqdomain_map()
1548 mutex_lock(&pcs->mutex); in pcs_irqdomain_map()
1549 list_add_tail(&pcswi->node, &pcs->irqs); in pcs_irqdomain_map()
1550 mutex_unlock(&pcs->mutex); in pcs_irqdomain_map()
1553 irq_set_chip_and_handler(irq, &pcs->chip, in pcs_irqdomain_map()
1567 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1574 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_init_chained_handler()
1578 if (!pcs_soc->irq_enable_mask || in pcs_irq_init_chained_handler()
1579 !pcs_soc->irq_status_mask) { in pcs_irq_init_chained_handler()
1580 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1581 return -EINVAL; in pcs_irq_init_chained_handler()
1584 INIT_LIST_HEAD(&pcs->irqs); in pcs_irq_init_chained_handler()
1585 pcs->chip.name = name; in pcs_irq_init_chained_handler()
1586 pcs->chip.irq_ack = pcs_irq_mask; in pcs_irq_init_chained_handler()
1587 pcs->chip.irq_mask = pcs_irq_mask; in pcs_irq_init_chained_handler()
1588 pcs->chip.irq_unmask = pcs_irq_unmask; in pcs_irq_init_chained_handler()
1589 pcs->chip.irq_set_wake = pcs_irq_set_wake; in pcs_irq_init_chained_handler()
1594 res = request_irq(pcs_soc->irq, pcs_irq_handler, in pcs_irq_init_chained_handler()
1599 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1603 irq_set_chained_handler_and_data(pcs_soc->irq, in pcs_irq_init_chained_handler()
1614 num_irqs = pcs->size; in pcs_irq_init_chained_handler()
1616 pcs->domain = irq_domain_add_simple(np, num_irqs, 0, in pcs_irq_init_chained_handler()
1619 if (!pcs->domain) { in pcs_irq_init_chained_handler()
1620 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_init_chained_handler()
1621 return -EINVAL; in pcs_irq_init_chained_handler()
1635 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_save_context()
1637 if (!pcs->saved_vals) { in pcs_save_context()
1638 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); in pcs_save_context()
1639 if (!pcs->saved_vals) in pcs_save_context()
1640 return -ENOMEM; in pcs_save_context()
1643 switch (pcs->width) { in pcs_save_context()
1645 regsl = pcs->saved_vals; in pcs_save_context()
1646 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1647 *regsl++ = pcs->read(pcs->base + i); in pcs_save_context()
1650 regsw = pcs->saved_vals; in pcs_save_context()
1651 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1652 *regsw++ = pcs->read(pcs->base + i); in pcs_save_context()
1655 regshw = pcs->saved_vals; in pcs_save_context()
1656 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1657 *regshw++ = pcs->read(pcs->base + i); in pcs_save_context()
1671 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_restore_context()
1673 switch (pcs->width) { in pcs_restore_context()
1675 regsl = pcs->saved_vals; in pcs_restore_context()
1676 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1677 pcs->write(*regsl++, pcs->base + i); in pcs_restore_context()
1680 regsw = pcs->saved_vals; in pcs_restore_context()
1681 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1682 pcs->write(*regsw++, pcs->base + i); in pcs_restore_context()
1685 regshw = pcs->saved_vals; in pcs_restore_context()
1686 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1687 pcs->write(*regshw++, pcs->base + i); in pcs_restore_context()
1699 return -EINVAL; in pinctrl_single_suspend()
1701 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { in pinctrl_single_suspend()
1709 return pinctrl_force_sleep(pcs->pctl); in pinctrl_single_suspend()
1718 return -EINVAL; in pinctrl_single_resume()
1720 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) in pinctrl_single_resume()
1723 return pinctrl_force_default(pcs->pctl); in pinctrl_single_resume()
1728 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1733 * Handle legacy binding with no #pinctrl-cells. This should be
1734 * always two pinctrl-single,bit-per-mux and one for others.
1742 const char *name = "#pinctrl-cells"; in pcs_quirk_missing_pinctrl_cells()
1750 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", in pcs_quirk_missing_pinctrl_cells()
1753 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1755 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1757 p->length = sizeof(__be32); in pcs_quirk_missing_pinctrl_cells()
1758 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1759 if (!p->value) in pcs_quirk_missing_pinctrl_cells()
1760 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1761 *(__be32 *)p->value = cpu_to_be32(cells); in pcs_quirk_missing_pinctrl_cells()
1763 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1764 if (!p->name) in pcs_quirk_missing_pinctrl_cells()
1765 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1767 pcs->missing_nr_pinctrl_cells = p; in pcs_quirk_missing_pinctrl_cells()
1770 error = of_add_property(np, pcs->missing_nr_pinctrl_cells); in pcs_quirk_missing_pinctrl_cells()
1778 struct device_node *np = pdev->dev.of_node; in pcs_probe()
1785 soc = of_device_get_match_data(&pdev->dev); in pcs_probe()
1787 return -EINVAL; in pcs_probe()
1789 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); in pcs_probe()
1791 return -ENOMEM; in pcs_probe()
1793 pcs->dev = &pdev->dev; in pcs_probe()
1794 pcs->np = np; in pcs_probe()
1795 raw_spin_lock_init(&pcs->lock); in pcs_probe()
1796 mutex_init(&pcs->mutex); in pcs_probe()
1797 INIT_LIST_HEAD(&pcs->gpiofuncs); in pcs_probe()
1798 pcs->flags = soc->flags; in pcs_probe()
1799 memcpy(&pcs->socdata, soc, sizeof(*soc)); in pcs_probe()
1801 ret = of_property_read_u32(np, "pinctrl-single,register-width", in pcs_probe()
1802 &pcs->width); in pcs_probe()
1804 dev_err(pcs->dev, "register width not specified\n"); in pcs_probe()
1809 ret = of_property_read_u32(np, "pinctrl-single,function-mask", in pcs_probe()
1810 &pcs->fmask); in pcs_probe()
1812 pcs->fshift = __ffs(pcs->fmask); in pcs_probe()
1813 pcs->fmax = pcs->fmask >> pcs->fshift; in pcs_probe()
1816 pcs->fmask = 0; in pcs_probe()
1817 pcs->fshift = 0; in pcs_probe()
1818 pcs->fmax = 0; in pcs_probe()
1821 ret = of_property_read_u32(np, "pinctrl-single,function-off", in pcs_probe()
1822 &pcs->foff); in pcs_probe()
1824 pcs->foff = PCS_OFF_DISABLED; in pcs_probe()
1826 pcs->bits_per_mux = of_property_read_bool(np, in pcs_probe()
1827 "pinctrl-single,bit-per-mux"); in pcs_probe()
1829 pcs->bits_per_mux ? 2 : 1); in pcs_probe()
1831 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); in pcs_probe()
1838 dev_err(pcs->dev, "could not get resource\n"); in pcs_probe()
1839 return -ENODEV; in pcs_probe()
1842 pcs->res = devm_request_mem_region(pcs->dev, res->start, in pcs_probe()
1844 if (!pcs->res) { in pcs_probe()
1845 dev_err(pcs->dev, "could not get mem_region\n"); in pcs_probe()
1846 return -EBUSY; in pcs_probe()
1849 pcs->size = resource_size(pcs->res); in pcs_probe()
1850 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); in pcs_probe()
1851 if (!pcs->base) { in pcs_probe()
1852 dev_err(pcs->dev, "could not ioremap\n"); in pcs_probe()
1853 return -ENODEV; in pcs_probe()
1858 switch (pcs->width) { in pcs_probe()
1860 pcs->read = pcs_readb; in pcs_probe()
1861 pcs->write = pcs_writeb; in pcs_probe()
1864 pcs->read = pcs_readw; in pcs_probe()
1865 pcs->write = pcs_writew; in pcs_probe()
1868 pcs->read = pcs_readl; in pcs_probe()
1869 pcs->write = pcs_writel; in pcs_probe()
1875 pcs->desc.name = DRIVER_NAME; in pcs_probe()
1876 pcs->desc.pctlops = &pcs_pinctrl_ops; in pcs_probe()
1877 pcs->desc.pmxops = &pcs_pinmux_ops; in pcs_probe()
1879 pcs->desc.confops = &pcs_pinconf_ops; in pcs_probe()
1880 pcs->desc.owner = THIS_MODULE; in pcs_probe()
1886 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl); in pcs_probe()
1888 dev_err(pcs->dev, "could not register single pinctrl driver\n"); in pcs_probe()
1896 pcs->socdata.irq = irq_of_parse_and_map(np, 0); in pcs_probe()
1897 if (pcs->socdata.irq) in pcs_probe()
1898 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1901 pdata = dev_get_platdata(&pdev->dev); in pcs_probe()
1903 if (pdata->rearm) in pcs_probe()
1904 pcs->socdata.rearm = pdata->rearm; in pcs_probe()
1905 if (pdata->irq) { in pcs_probe()
1906 pcs->socdata.irq = pdata->irq; in pcs_probe()
1907 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1914 dev_warn(pcs->dev, "initialized with no interrupts\n"); in pcs_probe()
1917 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); in pcs_probe()
1919 return pinctrl_enable(pcs->pctl); in pcs_probe()
1964 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1965 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1966 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1967 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1968 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1969 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1970 { .compatible = "pinconf-single", .data = &pinconf_single },
1991 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");