1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pinctrl/pinconf-generic.h>
23 #include "pinctrl-utils.h"
26 #define PADS_SCHMITT_EN_REG(pin)	(PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))  argument
27 #define PADS_SCHMITT_EN_BIT(pin)	BIT((pin) % 32)  argument
30 #define PADS_PU_PD_REG(pin)		(PADS_PU_PD0 + 0x4 * ((pin) / 16))  argument
31 #define PADS_PU_PD_SHIFT(pin)		(2 * ((pin) % 16))  argument
44 #define PADS_SLEW_RATE_REG(pin)		(PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))  argument
45 #define PADS_SLEW_RATE_BIT(pin)		BIT((pin) % 32)  argument
48 #define PADS_DRIVE_STRENGTH_REG(pin)					\  argument
49 	(PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
50 #define PADS_DRIVE_STRENGTH_SHIFT(pin)	(2 * ((pin) % 16))  argument
86 	unsigned int pin;  member
512 	PISTACHIO_FUNCTION_NONE = -1,
637 		.pin = PISTACHIO_PIN_##_pin,			\
643 		.mux_reg = -1,					\
644 		.mux_shift = -1,				\
645 		.mux_mask = -1,					\
651 		.pin = PISTACHIO_PIN_MFIO(_pin),		\
657 		.mux_reg = -1,					\
658 		.mux_shift = -1,				\
659 		.mux_mask = -1,					\
665 		.pin = PISTACHIO_PIN_MFIO(_pin),			\
833 	return readl(pctl->base + reg);  in pctl_readl()
836 static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)  in pctl_writel()  argument
838 	writel(val, pctl->base + reg);  in pctl_writel()
848 	return readl(bank->base + reg);  in gpio_readl()
851 static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,  in gpio_writel()  argument
854 	writel(val, bank->base + reg);  in gpio_writel()
858 				    u32 reg, unsigned int bit, u32 val)  in gpio_mask_writel()  argument
864 	gpio_writel(bank, (0x10000 | val) << bit, reg);  in gpio_mask_writel()
883 	return pctl->ngroups;  in pistachio_pinctrl_get_groups_count()
891 	return pctl->groups[group].name;  in pistachio_pinctrl_get_group_name()
901 	*pins = &pctl->groups[group].pin;  in pistachio_pinctrl_get_group_pins()
919 	return pctl->nfunctions;  in pistachio_pinmux_get_functions_count()
927 	return pctl->functions[func].name;  in pistachio_pinmux_get_function_name()
937 	*groups = pctl->functions[func].groups;  in pistachio_pinmux_get_function_groups()
938 	*num_groups = pctl->functions[func].ngroups;  in pistachio_pinmux_get_function_groups()
947 	const struct pistachio_pin_group *pg = &pctl->groups[group];  in pistachio_pinmux_enable()
948 	const struct pistachio_function *pf = &pctl->functions[func];  in pistachio_pinmux_enable()
951 	u32 val;  in pistachio_pinmux_enable()  local
953 	if (pg->mux_reg > 0) {  in pistachio_pinmux_enable()
954 		for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) {  in pistachio_pinmux_enable()
955 			if (pg->mux_option[i] == func)  in pistachio_pinmux_enable()
958 		if (i == ARRAY_SIZE(pg->mux_option)) {  in pistachio_pinmux_enable()
959 			dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",  in pistachio_pinmux_enable()
961 			return -EINVAL;  in pistachio_pinmux_enable()
964 		val = pctl_readl(pctl, pg->mux_reg);  in pistachio_pinmux_enable()
965 		val &= ~(pg->mux_mask << pg->mux_shift);  in pistachio_pinmux_enable()
966 		val |= i << pg->mux_shift;  in pistachio_pinmux_enable()
967 		pctl_writel(pctl, val, pg->mux_reg);  in pistachio_pinmux_enable()
969 		if (pf->scenarios) {  in pistachio_pinmux_enable()
970 			for (i = 0; i < pf->nscenarios; i++) {  in pistachio_pinmux_enable()
971 				if (pf->scenarios[i] == group)  in pistachio_pinmux_enable()
974 			if (WARN_ON(i == pf->nscenarios))  in pistachio_pinmux_enable()
975 				return -EINVAL;  in pistachio_pinmux_enable()
977 			val = pctl_readl(pctl, pf->scenario_reg);  in pistachio_pinmux_enable()
978 			val &= ~(pf->scenario_mask << pf->scenario_shift);  in pistachio_pinmux_enable()
979 			val |= i << pf->scenario_shift;  in pistachio_pinmux_enable()
980 			pctl_writel(pctl, val, pf->scenario_reg);  in pistachio_pinmux_enable()
984 	range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);  in pistachio_pinmux_enable()
986 		gpio_disable(gpiochip_get_data(range->gc), pg->pin - range->pin_base);  in pistachio_pinmux_enable()
998 static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,  in pistachio_pinconf_get()  argument
1003 	u32 val, arg;  in pistachio_pinconf_get()  local
1007 		val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));  in pistachio_pinconf_get()
1008 		arg = !!(val & PADS_SCHMITT_EN_BIT(pin));  in pistachio_pinconf_get()
1011 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1012 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1013 		arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;  in pistachio_pinconf_get()
1016 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1017 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1018 		arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;  in pistachio_pinconf_get()
1021 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1022 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1023 		arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;  in pistachio_pinconf_get()
1026 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>  in pistachio_pinconf_get()
1027 			PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_get()
1028 		arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;  in pistachio_pinconf_get()
1031 		val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));  in pistachio_pinconf_get()
1032 		arg = !!(val & PADS_SLEW_RATE_BIT(pin));  in pistachio_pinconf_get()
1035 		val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>  in pistachio_pinconf_get()
1036 			PADS_DRIVE_STRENGTH_SHIFT(pin);  in pistachio_pinconf_get()
1037 		switch (val & PADS_DRIVE_STRENGTH_MASK) {  in pistachio_pinconf_get()
1054 		dev_dbg(pctl->dev, "Property %u not supported\n", param);  in pistachio_pinconf_get()
1055 		return -ENOTSUPP;  in pistachio_pinconf_get()
1063 static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,  in pistachio_pinconf_set()  argument
1068 	u32 drv, val, arg;  in pistachio_pinconf_set()  local
1077 			val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));  in pistachio_pinconf_set()
1079 				val |= PADS_SCHMITT_EN_BIT(pin);  in pistachio_pinconf_set()
1081 				val &= ~PADS_SCHMITT_EN_BIT(pin);  in pistachio_pinconf_set()
1082 			pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));  in pistachio_pinconf_set()
1085 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1086 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1087 			val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1088 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1091 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1092 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1093 			val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1094 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1097 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1098 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1099 			val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1100 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1103 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1104 			val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));  in pistachio_pinconf_set()
1105 			val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);  in pistachio_pinconf_set()
1106 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));  in pistachio_pinconf_set()
1109 			val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));  in pistachio_pinconf_set()
1111 				val |= PADS_SLEW_RATE_BIT(pin);  in pistachio_pinconf_set()
1113 				val &= ~PADS_SLEW_RATE_BIT(pin);  in pistachio_pinconf_set()
1114 			pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));  in pistachio_pinconf_set()
1117 			val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));  in pistachio_pinconf_set()
1118 			val &= ~(PADS_DRIVE_STRENGTH_MASK <<  in pistachio_pinconf_set()
1119 				 PADS_DRIVE_STRENGTH_SHIFT(pin));  in pistachio_pinconf_set()
1134 				dev_err(pctl->dev,  in pistachio_pinconf_set()
1137 				return -EINVAL;  in pistachio_pinconf_set()
1139 			val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);  in pistachio_pinconf_set()
1140 			pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));  in pistachio_pinconf_set()
1143 			dev_err(pctl->dev, "Property %u not supported\n",  in pistachio_pinconf_set()
1145 			return -ENOTSUPP;  in pistachio_pinconf_set()
1159 	.name = "pistachio-pinctrl",
1223 	gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);  in pistachio_gpio_irq_ack()
1230 	gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);  in pistachio_gpio_irq_mask()
1237 	gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);  in pistachio_gpio_irq_unmask()
1244 	pistachio_gpio_direction_input(chip, data->hwirq);  in pistachio_gpio_irq_startup()
1256 		gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);  in pistachio_gpio_irq_set_type()
1257 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1259 		gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,  in pistachio_gpio_irq_set_type()
1263 		gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);  in pistachio_gpio_irq_set_type()
1264 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1266 		gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,  in pistachio_gpio_irq_set_type()
1270 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1272 		gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,  in pistachio_gpio_irq_set_type()
1276 		gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);  in pistachio_gpio_irq_set_type()
1277 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1281 		gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);  in pistachio_gpio_irq_set_type()
1282 		gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,  in pistachio_gpio_irq_set_type()
1286 		return -EINVAL;  in pistachio_gpio_irq_set_type()
1303 	unsigned int pin;  in pistachio_gpio_irq_handler()  local
1308 	for_each_set_bit(pin, &pending, 16)  in pistachio_gpio_irq_handler()
1309 		generic_handle_domain_irq(gc->irq.domain, pin);  in pistachio_gpio_irq_handler()
1354 	for (i = 0; i < pctl->nbanks; i++) {  in pistachio_gpio_register()
1360 		child = device_get_named_child_node(pctl->dev, child_name);  in pistachio_gpio_register()
1362 			dev_err(pctl->dev, "No node for bank %u\n", i);  in pistachio_gpio_register()
1363 			ret = -ENODEV;  in pistachio_gpio_register()
1367 		if (!fwnode_property_present(child, "gpio-controller")) {  in pistachio_gpio_register()
1369 			dev_err(pctl->dev,  in pistachio_gpio_register()
1370 				"No gpio-controller property for bank %u\n", i);  in pistachio_gpio_register()
1371 			ret = -ENODEV;  in pistachio_gpio_register()
1378 			dev_err(pctl->dev, "Failed to retrieve IRQ for bank %u\n", i);  in pistachio_gpio_register()
1383 			dev_err(pctl->dev, "No IRQ for bank %u\n", i);  in pistachio_gpio_register()
1384 			ret = -EINVAL;  in pistachio_gpio_register()
1389 		bank = &pctl->gpio_banks[i];  in pistachio_gpio_register()
1390 		bank->pctl = pctl;  in pistachio_gpio_register()
1391 		bank->base = pctl->base + GPIO_BANK_BASE(i);  in pistachio_gpio_register()
1393 		bank->gpio_chip.parent = pctl->dev;  in pistachio_gpio_register()
1394 		bank->gpio_chip.fwnode = child;  in pistachio_gpio_register()
1396 		girq = &bank->gpio_chip.irq;  in pistachio_gpio_register()
1397 		girq->chip = &bank->irq_chip;  in pistachio_gpio_register()
1398 		girq->parent_handler = pistachio_gpio_irq_handler;  in pistachio_gpio_register()
1399 		girq->num_parents = 1;  in pistachio_gpio_register()
1400 		girq->parents = devm_kcalloc(pctl->dev, 1,  in pistachio_gpio_register()
1401 					     sizeof(*girq->parents),  in pistachio_gpio_register()
1403 		if (!girq->parents) {  in pistachio_gpio_register()
1404 			ret = -ENOMEM;  in pistachio_gpio_register()
1407 		girq->parents[0] = irq;  in pistachio_gpio_register()
1408 		girq->default_type = IRQ_TYPE_NONE;  in pistachio_gpio_register()
1409 		girq->handler = handle_level_irq;  in pistachio_gpio_register()
1411 		ret = gpiochip_add_data(&bank->gpio_chip, bank);  in pistachio_gpio_register()
1413 			dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",  in pistachio_gpio_register()
1418 		ret = gpiochip_add_pin_range(&bank->gpio_chip,  in pistachio_gpio_register()
1419 					     dev_name(pctl->dev), 0,  in pistachio_gpio_register()
1420 					     bank->pin_base, bank->npins);  in pistachio_gpio_register()
1422 			dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",  in pistachio_gpio_register()
1424 			gpiochip_remove(&bank->gpio_chip);  in pistachio_gpio_register()
1431 	for (; i > 0; i--) {  in pistachio_gpio_register()
1432 		bank = &pctl->gpio_banks[i - 1];  in pistachio_gpio_register()
1433 		gpiochip_remove(&bank->gpio_chip);  in pistachio_gpio_register()
1439 	{ .compatible = "img,pistachio-system-pinctrl", },
1447 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);  in pistachio_pinctrl_probe()
1449 		return -ENOMEM;  in pistachio_pinctrl_probe()
1450 	pctl->dev = &pdev->dev;  in pistachio_pinctrl_probe()
1451 	dev_set_drvdata(&pdev->dev, pctl);  in pistachio_pinctrl_probe()
1453 	pctl->base = devm_platform_ioremap_resource(pdev, 0);  in pistachio_pinctrl_probe()
1454 	if (IS_ERR(pctl->base))  in pistachio_pinctrl_probe()
1455 		return PTR_ERR(pctl->base);  in pistachio_pinctrl_probe()
1457 	pctl->pins = pistachio_pins;  in pistachio_pinctrl_probe()
1458 	pctl->npins = ARRAY_SIZE(pistachio_pins);  in pistachio_pinctrl_probe()
1459 	pctl->functions = pistachio_functions;  in pistachio_pinctrl_probe()
1460 	pctl->nfunctions = ARRAY_SIZE(pistachio_functions);  in pistachio_pinctrl_probe()
1461 	pctl->groups = pistachio_groups;  in pistachio_pinctrl_probe()
1462 	pctl->ngroups = ARRAY_SIZE(pistachio_groups);  in pistachio_pinctrl_probe()
1463 	pctl->gpio_banks = pistachio_gpio_banks;  in pistachio_pinctrl_probe()
1464 	pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);  in pistachio_pinctrl_probe()
1466 	pistachio_pinctrl_desc.pins = pctl->pins;  in pistachio_pinctrl_probe()
1467 	pistachio_pinctrl_desc.npins = pctl->npins;  in pistachio_pinctrl_probe()
1469 	pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,  in pistachio_pinctrl_probe()
1471 	if (IS_ERR(pctl->pctldev)) {  in pistachio_pinctrl_probe()
1472 		dev_err(&pdev->dev, "Failed to register pinctrl device\n");  in pistachio_pinctrl_probe()
1473 		return PTR_ERR(pctl->pctldev);  in pistachio_pinctrl_probe()
1481 		.name = "pistachio-pinctrl",