Lines Matching +full:clr +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-or-later
136 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
137 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
142 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
147 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr()
148 regmap_get_reg_stride(priv->regs); in sgpio_get_addr()
157 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl()
169 ret = regmap_write(priv->regs, addr, val); in sgpio_writel()
179 ret = regmap_update_bits(priv->regs, addr, clear | set, set); in sgpio_clrsetbits()
185 int width = priv->bitcount - 1; in sgpio_configure_bitstream()
186 u32 clr, set; in sgpio_configure_bitstream() local
188 switch (priv->properties->arch) { in sgpio_configure_bitstream()
190 clr = SGPIO_LUTON_PORT_WIDTH; in sgpio_configure_bitstream()
195 clr = SGPIO_OCELOT_PORT_WIDTH; in sgpio_configure_bitstream()
200 clr = SGPIO_SPARX5_PORT_WIDTH; in sgpio_configure_bitstream()
207 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); in sgpio_configure_bitstream()
212 u32 clr, set; in sgpio_configure_clock() local
214 switch (priv->properties->arch) { in sgpio_configure_clock()
216 clr = SGPIO_LUTON_CLK_FREQ; in sgpio_configure_clock()
220 clr = SGPIO_OCELOT_CLK_FREQ; in sgpio_configure_clock()
224 clr = SGPIO_SPARX5_CLK_FREQ; in sgpio_configure_clock()
230 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); in sgpio_configure_clock()
241 switch (priv->properties->arch) { in sgpio_single_shot()
254 return -EINVAL; in sgpio_single_shot()
265 mutex_lock(&priv->poll_lock); in sgpio_single_shot()
266 ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat, in sgpio_single_shot()
271 ret = regmap_read_poll_timeout(priv->regs, addr, ctrl, in sgpio_single_shot()
275 ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat); in sgpio_single_shot()
277 mutex_unlock(&priv->poll_lock); in sgpio_single_shot()
286 unsigned int bit = SGPIO_SRC_BITS * addr->bit; in sgpio_output_set()
287 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port); in sgpio_output_set()
289 u32 clr, set; in sgpio_output_set() local
292 switch (priv->properties->arch) { in sgpio_output_set()
294 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); in sgpio_output_set()
298 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); in sgpio_output_set()
302 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); in sgpio_output_set()
306 return -EINVAL; in sgpio_output_set()
309 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set, in sgpio_output_set()
326 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); in sgpio_output_get()
327 unsigned int bit = SGPIO_SRC_BITS * addr->bit; in sgpio_output_get()
329 switch (priv->properties->arch) { in sgpio_output_get()
349 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); in sgpio_input_get()
357 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_get()
365 val = bank->is_input; in sgpio_pinconf_get()
369 val = !bank->is_input; in sgpio_pinconf_get()
373 if (bank->is_input) in sgpio_pinconf_get()
374 return -EINVAL; in sgpio_pinconf_get()
379 return -ENOTSUPP; in sgpio_pinconf_get()
391 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_set()
404 if (bank->is_input) in sgpio_pinconf_set()
405 return -EINVAL; in sgpio_pinconf_set()
410 err = -ENOTSUPP; in sgpio_pinconf_set()
458 return (input == bank->is_input) ? 0 : -EINVAL; in sgpio_gpio_set_direction()
466 struct sgpio_priv *priv = bank->priv; in sgpio_gpio_request_enable()
471 if ((priv->ports & BIT(addr.port)) == 0) { in sgpio_gpio_request_enable()
472 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", in sgpio_gpio_request_enable()
474 return -EINVAL; in sgpio_gpio_request_enable()
493 return bank->pctl_desc.npins; in sgpio_pctl_get_groups_count()
501 return bank->pctl_desc.pins[group].name; in sgpio_pctl_get_group_name()
511 *pins = &bank->pctl_desc.pins[group].number; in sgpio_pctl_get_group_pins()
529 /* Fixed-position function */ in microchip_sgpio_direction_input()
530 return bank->is_input ? 0 : -EINVAL; in microchip_sgpio_direction_input()
537 struct sgpio_priv *priv = bank->priv; in microchip_sgpio_direction_output()
540 /* Fixed-position function */ in microchip_sgpio_direction_output()
541 if (bank->is_input) in microchip_sgpio_direction_output()
542 return -EINVAL; in microchip_sgpio_direction_output()
553 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; in microchip_sgpio_get_direction()
565 struct sgpio_priv *priv = bank->priv; in microchip_sgpio_get_value()
570 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); in microchip_sgpio_get_value()
578 struct sgpio_priv *priv = bank->priv; in microchip_sgpio_of_xlate()
585 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || in microchip_sgpio_of_xlate()
586 gpiospec->args[1] > priv->bitcount) in microchip_sgpio_of_xlate()
587 return -EINVAL; in microchip_sgpio_of_xlate()
589 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); in microchip_sgpio_of_xlate()
591 if (pin > gc->ngpio) in microchip_sgpio_of_xlate()
592 return -EINVAL; in microchip_sgpio_of_xlate()
595 *flags = gpiospec->args[2]; in microchip_sgpio_of_xlate()
602 const char *range_property_name = "microchip,sgpio-port-ranges"; in microchip_sgpio_get_ports()
603 struct device *dev = priv->dev; in microchip_sgpio_get_ports()
611 nranges == -EINVAL ? "Missing" : "Invalid", in microchip_sgpio_get_ports()
613 return -EINVAL; in microchip_sgpio_get_ports()
629 dev_err(dev, "Ill-formed port-range [%d:%d]\n", in microchip_sgpio_get_ports()
632 priv->ports |= GENMASK(end, start); in microchip_sgpio_get_ports()
649 sgpio_pin_to_addr(bank->priv, gpio, &addr); in microchip_sgpio_irq_settype()
651 spin_lock_irqsave(&bank->priv->lock, flags); in microchip_sgpio_irq_settype()
654 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); in microchip_sgpio_irq_settype()
655 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); in microchip_sgpio_irq_settype()
658 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, in microchip_sgpio_irq_settype()
660 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, in microchip_sgpio_irq_settype()
664 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, in microchip_sgpio_irq_settype()
667 /* Possibly re-enable interrupts */ in microchip_sgpio_irq_settype()
668 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); in microchip_sgpio_irq_settype()
670 spin_unlock_irqrestore(&bank->priv->lock, flags); in microchip_sgpio_irq_settype()
682 sgpio_pin_to_addr(bank->priv, gpio, &addr); in microchip_sgpio_irq_setreg()
685 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); in microchip_sgpio_irq_setreg()
687 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); in microchip_sgpio_irq_setreg()
695 gpiochip_disable_irq(chip, data->hwirq); in microchip_sgpio_irq_mask()
702 gpiochip_enable_irq(chip, data->hwirq); in microchip_sgpio_irq_unmask()
713 sgpio_pin_to_addr(bank->priv, gpio, &addr); in microchip_sgpio_irq_ack()
715 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit); in microchip_sgpio_irq_ack()
744 return -EINVAL; in microchip_sgpio_irq_set_type()
765 struct sgpio_priv *priv = bank->priv; in sgpio_irq_handler()
769 for (bit = 0; bit < priv->bitcount; bit++) { in sgpio_irq_handler()
778 generic_handle_domain_irq(chip->irq.domain, gpio); in sgpio_irq_handler()
799 bank = (bankno == 0) ? &priv->in : &priv->out; in microchip_sgpio_register_bank()
800 bank->priv = priv; in microchip_sgpio_register_bank()
803 dev_info(dev, "failed to get number of gpios for bank%d\n", in microchip_sgpio_register_bank()
808 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; in microchip_sgpio_register_bank()
809 if (priv->bitcount > SGPIO_MAX_BITS) { in microchip_sgpio_register_bank()
812 return -EINVAL; in microchip_sgpio_register_bank()
815 pctl_desc = &bank->pctl_desc; in microchip_sgpio_register_bank()
816 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", in microchip_sgpio_register_bank()
818 bank->is_input ? "in" : "out"); in microchip_sgpio_register_bank()
819 pctl_desc->pctlops = &sgpio_pctl_ops; in microchip_sgpio_register_bank()
820 pctl_desc->pmxops = &sgpio_pmx_ops; in microchip_sgpio_register_bank()
821 pctl_desc->confops = &sgpio_confops; in microchip_sgpio_register_bank()
822 pctl_desc->owner = THIS_MODULE; in microchip_sgpio_register_bank()
826 return -ENOMEM; in microchip_sgpio_register_bank()
828 pctl_desc->npins = ngpios; in microchip_sgpio_register_bank()
829 pctl_desc->pins = pins; in microchip_sgpio_register_bank()
839 bank->is_input ? 'I' : 'O', in microchip_sgpio_register_bank()
842 return -ENOMEM; in microchip_sgpio_register_bank()
849 gc = &bank->gpio; in microchip_sgpio_register_bank()
850 gc->label = pctl_desc->name; in microchip_sgpio_register_bank()
851 gc->parent = dev; in microchip_sgpio_register_bank()
852 gc->fwnode = fwnode; in microchip_sgpio_register_bank()
853 gc->owner = THIS_MODULE; in microchip_sgpio_register_bank()
854 gc->get_direction = microchip_sgpio_get_direction; in microchip_sgpio_register_bank()
855 gc->direction_input = microchip_sgpio_direction_input; in microchip_sgpio_register_bank()
856 gc->direction_output = microchip_sgpio_direction_output; in microchip_sgpio_register_bank()
857 gc->get = microchip_sgpio_get_value; in microchip_sgpio_register_bank()
858 gc->set = microchip_sgpio_set_value; in microchip_sgpio_register_bank()
859 gc->request = gpiochip_generic_request; in microchip_sgpio_register_bank()
860 gc->free = gpiochip_generic_free; in microchip_sgpio_register_bank()
861 gc->of_xlate = microchip_sgpio_of_xlate; in microchip_sgpio_register_bank()
862 gc->of_gpio_n_cells = 3; in microchip_sgpio_register_bank()
863 gc->base = -1; in microchip_sgpio_register_bank()
864 gc->ngpio = ngpios; in microchip_sgpio_register_bank()
865 gc->can_sleep = !bank->is_input; in microchip_sgpio_register_bank()
867 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { in microchip_sgpio_register_bank()
872 struct gpio_irq_chip *girq = &gc->irq; in microchip_sgpio_register_bank()
875 girq->parent_handler = sgpio_irq_handler; in microchip_sgpio_register_bank()
876 girq->num_parents = 1; in microchip_sgpio_register_bank()
877 girq->parents = devm_kcalloc(dev, 1, in microchip_sgpio_register_bank()
878 sizeof(*girq->parents), in microchip_sgpio_register_bank()
880 if (!girq->parents) in microchip_sgpio_register_bank()
881 return -ENOMEM; in microchip_sgpio_register_bank()
882 girq->parents[0] = irq; in microchip_sgpio_register_bank()
883 girq->default_type = IRQ_TYPE_NONE; in microchip_sgpio_register_bank()
884 girq->handler = handle_bad_irq; in microchip_sgpio_register_bank()
904 struct device *dev = &pdev->dev; in microchip_sgpio_probe()
918 return -ENOMEM; in microchip_sgpio_probe()
920 priv->dev = dev; in microchip_sgpio_probe()
921 spin_lock_init(&priv->lock); in microchip_sgpio_probe()
922 mutex_init(&priv->poll_lock); in microchip_sgpio_probe()
924 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); in microchip_sgpio_probe()
934 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) in microchip_sgpio_probe()
935 priv->clock = 12500000; in microchip_sgpio_probe()
936 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { in microchip_sgpio_probe()
937 dev_err(dev, "Invalid frequency %d\n", priv->clock); in microchip_sgpio_probe()
938 return -EINVAL; in microchip_sgpio_probe()
941 priv->regs = ocelot_regmap_from_resource(pdev, 0, ®map_config); in microchip_sgpio_probe()
942 if (IS_ERR(priv->regs)) in microchip_sgpio_probe()
943 return PTR_ERR(priv->regs); in microchip_sgpio_probe()
945 priv->properties = device_get_match_data(dev); in microchip_sgpio_probe()
946 priv->in.is_input = true; in microchip_sgpio_probe()
956 return -EINVAL; in microchip_sgpio_probe()
968 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { in microchip_sgpio_probe()
970 return -ERANGE; in microchip_sgpio_probe()
975 val = max(2U, div_clock / priv->clock); in microchip_sgpio_probe()
980 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); in microchip_sgpio_probe()
987 .compatible = "microchip,sparx5-sgpio",
990 .compatible = "mscc,luton-sgpio",
993 .compatible = "mscc,ocelot-sgpio",
1003 .name = "pinctrl-microchip-sgpio",