1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinmux.h>
18 #include "pinmux.h"
19 #include "pinctrl-equilibrium.h"
21 #define PIN_NAME_FMT	"io-%d"
32 	raw_spin_lock_irqsave(&gctrl->lock, flags);  in eqbr_gpio_disable_irq()
33 	writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);  in eqbr_gpio_disable_irq()
34 	raw_spin_unlock_irqrestore(&gctrl->lock, flags);  in eqbr_gpio_disable_irq()
44 	gc->direction_input(gc, offset);  in eqbr_gpio_enable_irq()
45 	raw_spin_lock_irqsave(&gctrl->lock, flags);  in eqbr_gpio_enable_irq()
46 	writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);  in eqbr_gpio_enable_irq()
47 	raw_spin_unlock_irqrestore(&gctrl->lock, flags);  in eqbr_gpio_enable_irq()
57 	raw_spin_lock_irqsave(&gctrl->lock, flags);  in eqbr_gpio_ack_irq()
58 	writel(BIT(offset), gctrl->membase + GPIO_IRNCR);  in eqbr_gpio_ack_irq()
59 	raw_spin_unlock_irqrestore(&gctrl->lock, flags);  in eqbr_gpio_ack_irq()
83 	raw_spin_lock_irqsave(&gctrl->lock, flags);  in eqbr_irq_type_cfg()
84 	eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type);  in eqbr_irq_type_cfg()
85 	eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type);  in eqbr_irq_type_cfg()
86 	eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type);  in eqbr_irq_type_cfg()
87 	raw_spin_unlock_irqrestore(&gctrl->lock, flags);  in eqbr_irq_type_cfg()
136 		return -EINVAL;  in eqbr_gpio_set_irq_type()
156 	pins = readl(gctrl->membase + GPIO_IRNCR);  in eqbr_irq_handler()
158 	for_each_set_bit(offset, &pins, gc->ngpio)  in eqbr_irq_handler()
159 		generic_handle_domain_irq(gc->irq.domain, offset);  in eqbr_irq_handler()
169 	gc = &gctrl->chip;  in gpiochip_setup()
170 	gc->label = gctrl->name;  in gpiochip_setup()
171 	gc->fwnode = gctrl->fwnode;  in gpiochip_setup()
173 	if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) {  in gpiochip_setup()
175 			gctrl->name);  in gpiochip_setup()
179 	gctrl->ic.name = "gpio_irq";  in gpiochip_setup()
180 	gctrl->ic.irq_mask = eqbr_gpio_disable_irq;  in gpiochip_setup()
181 	gctrl->ic.irq_unmask = eqbr_gpio_enable_irq;  in gpiochip_setup()
182 	gctrl->ic.irq_ack = eqbr_gpio_ack_irq;  in gpiochip_setup()
183 	gctrl->ic.irq_mask_ack = eqbr_gpio_mask_ack_irq;  in gpiochip_setup()
184 	gctrl->ic.irq_set_type = eqbr_gpio_set_irq_type;  in gpiochip_setup()
186 	girq = &gctrl->chip.irq;  in gpiochip_setup()
187 	girq->chip = &gctrl->ic;  in gpiochip_setup()
188 	girq->parent_handler = eqbr_irq_handler;  in gpiochip_setup()
189 	girq->num_parents = 1;  in gpiochip_setup()
190 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL);  in gpiochip_setup()
191 	if (!girq->parents)  in gpiochip_setup()
192 		return -ENOMEM;  in gpiochip_setup()
194 	girq->default_type = IRQ_TYPE_NONE;  in gpiochip_setup()
195 	girq->handler = handle_bad_irq;  in gpiochip_setup()
196 	girq->parents[0] = gctrl->virq;  in gpiochip_setup()
203 	struct device *dev = drvdata->dev;  in gpiolib_reg()
209 	for (i = 0; i < drvdata->nr_gpio_ctrls; i++) {  in gpiolib_reg()
210 		gctrl = drvdata->gpio_ctrls + i;  in gpiolib_reg()
211 		np = to_of_node(gctrl->fwnode);  in gpiolib_reg()
213 		gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i);  in gpiolib_reg()
214 		if (!gctrl->name)  in gpiolib_reg()
215 			return -ENOMEM;  in gpiolib_reg()
219 			return -ENXIO;  in gpiolib_reg()
222 		gctrl->membase = devm_ioremap_resource(dev, &res);  in gpiolib_reg()
223 		if (IS_ERR(gctrl->membase))  in gpiolib_reg()
224 			return PTR_ERR(gctrl->membase);  in gpiolib_reg()
226 		gctrl->virq = irq_of_parse_and_map(np, 0);  in gpiolib_reg()
227 		if (!gctrl->virq) {  in gpiolib_reg()
229 				gctrl->name);  in gpiolib_reg()
230 			return -ENXIO;  in gpiolib_reg()
232 		raw_spin_lock_init(&gctrl->lock);  in gpiolib_reg()
234 		ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8,  in gpiolib_reg()
235 				 gctrl->membase + GPIO_IN,  in gpiolib_reg()
236 				 gctrl->membase + GPIO_OUTSET,  in gpiolib_reg()
237 				 gctrl->membase + GPIO_OUTCLR,  in gpiolib_reg()
238 				 gctrl->membase + GPIO_DIR,  in gpiolib_reg()
249 		ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl);  in gpiolib_reg()
263 	for (i = 0; i < pctl->nr_banks; i++) {  in find_pinbank_via_pin()
264 		bank = &pctl->pin_banks[i];  in find_pinbank_via_pin()
265 		if (pin >= bank->pin_base &&  in find_pinbank_via_pin()
266 		    (pin - bank->pin_base) < bank->nr_pins)  in find_pinbank_via_pin()
291 		dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);  in eqbr_set_pin_mux()
292 		return -ENODEV;  in eqbr_set_pin_mux()
294 	mem = bank->membase;  in eqbr_set_pin_mux()
295 	offset = pin - bank->pin_base;  in eqbr_set_pin_mux()
297 	if (!(bank->aval_pinmap & BIT(offset))) {  in eqbr_set_pin_mux()
298 		dev_err(pctl->dev,  in eqbr_set_pin_mux()
300 			pin, bank->pin_base, bank->aval_pinmap);  in eqbr_set_pin_mux()
301 		return -ENODEV;  in eqbr_set_pin_mux()
304 	raw_spin_lock_irqsave(&pctl->lock, flags);  in eqbr_set_pin_mux()
306 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in eqbr_set_pin_mux()
316 	unsigned int *pinmux;  in eqbr_pinmux_set_mux()  local
321 		return -EINVAL;  in eqbr_pinmux_set_mux()
325 		return -EINVAL;  in eqbr_pinmux_set_mux()
327 	pinmux = grp->data;  in eqbr_pinmux_set_mux()
328 	for (i = 0; i < grp->num_pins; i++)  in eqbr_pinmux_set_mux()
329 		eqbr_set_pin_mux(pctl, pinmux[i], grp->pins[i]);  in eqbr_pinmux_set_mux()
354 	unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/  in get_drv_cur()
366 	for (i = 0; i < pctl->nr_gpio_ctrls; i++) {  in get_gpio_ctrls_via_bank()
367 		if (pctl->gpio_ctrls[i].bank == bank)  in get_gpio_ctrls_via_bank()
368 			return &pctl->gpio_ctrls[i];  in get_gpio_ctrls_via_bank()
388 		dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);  in eqbr_pinconf_get()
389 		return -ENODEV;  in eqbr_pinconf_get()
391 	mem = bank->membase;  in eqbr_pinconf_get()
392 	offset = pin - bank->pin_base;  in eqbr_pinconf_get()
394 	if (!(bank->aval_pinmap & BIT(offset))) {  in eqbr_pinconf_get()
395 		dev_err(pctl->dev,  in eqbr_pinconf_get()
397 			pin, bank->pin_base, bank->aval_pinmap);  in eqbr_pinconf_get()
398 		return -ENODEV;  in eqbr_pinconf_get()
401 	raw_spin_lock_irqsave(&pctl->lock, flags);  in eqbr_pinconf_get()
421 			dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",  in eqbr_pinconf_get()
422 				bank->pin_base, pin);  in eqbr_pinconf_get()
423 			raw_spin_unlock_irqrestore(&pctl->lock, flags);  in eqbr_pinconf_get()
424 			return -ENODEV;  in eqbr_pinconf_get()
426 		val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset));  in eqbr_pinconf_get()
429 		raw_spin_unlock_irqrestore(&pctl->lock, flags);  in eqbr_pinconf_get()
430 		return -ENOTSUPP;  in eqbr_pinconf_get()
432 	raw_spin_unlock_irqrestore(&pctl->lock, flags);  in eqbr_pinconf_get()
458 			dev_err(pctl->dev,  in eqbr_pinconf_set()
460 			return -ENODEV;  in eqbr_pinconf_set()
462 		mem = bank->membase;  in eqbr_pinconf_set()
463 		offset = pin - bank->pin_base;  in eqbr_pinconf_set()
490 				dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",  in eqbr_pinconf_set()
491 					bank->pin_base, pin);  in eqbr_pinconf_set()
492 				return -ENODEV;  in eqbr_pinconf_set()
494 			gc = &gctrl->chip;  in eqbr_pinconf_set()
495 			gc->direction_output(gc, offset, 0);  in eqbr_pinconf_set()
498 			return -ENOTSUPP;  in eqbr_pinconf_set()
501 		raw_spin_lock_irqsave(&pctl->lock, flags);  in eqbr_pinconf_set()
505 		raw_spin_unlock_irqrestore(&pctl->lock, flags);  in eqbr_pinconf_set()
524 			return -ENOTSUPP;  in eqbr_pinconf_group_get()
527 			return -ENOTSUPP;  in eqbr_pinconf_group_get()
584 	struct device_node *node = dev->of_node;  in funcs_utils()
600 				(char *)prop->value);  in funcs_utils()
625 				funcs[fid].groups[j] = prop->value;  in funcs_utils()
631 			return -EINVAL;  in funcs_utils()
641 	struct device *dev = drvdata->dev;  in eqbr_build_functions()
652 		return -ENOMEM;  in eqbr_build_functions()
669 			return -ENOMEM;  in eqbr_build_functions()
682 		ret = pinmux_generic_add_function(drvdata->pctl_dev,  in eqbr_build_functions()
699 	struct device *dev = drvdata->dev;  in eqbr_build_groups()
700 	struct device_node *node = dev->of_node;  in eqbr_build_groups()
701 	unsigned int *pinmux, pin_id, pinmux_id;  in eqbr_build_groups()  local
714 			dev_err(dev, "No pins in the group: %s\n", prop->name);  in eqbr_build_groups()
716 			return -EINVAL;  in eqbr_build_groups()
718 		group.name = prop->value;  in eqbr_build_groups()
723 			return -ENOMEM;  in eqbr_build_groups()
726 		pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux),  in eqbr_build_groups()
728 		if (!pinmux) {  in eqbr_build_groups()
730 			return -ENOMEM;  in eqbr_build_groups()
735 				dev_err(dev, "Group %s: Read intel pins id failed\n",  in eqbr_build_groups()
738 				return -EINVAL;  in eqbr_build_groups()
740 			if (pin_id >= drvdata->pctl_desc.npins) {  in eqbr_build_groups()
741 				dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",  in eqbr_build_groups()
744 				return -EINVAL;  in eqbr_build_groups()
747 			if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {  in eqbr_build_groups()
748 				dev_err(dev, "Group %s: Read intel pinmux id failed\n",  in eqbr_build_groups()
751 				return -EINVAL;  in eqbr_build_groups()
753 			pinmux[j] = pinmux_id;  in eqbr_build_groups()
756 		err = pinctrl_generic_add_group(drvdata->pctl_dev, group.name,  in eqbr_build_groups()
758 						pinmux);  in eqbr_build_groups()
765 		pinmux = NULL;  in eqbr_build_groups()
780 	dev = drvdata->dev;  in pinctrl_reg()
781 	pctl_desc = &drvdata->pctl_desc;  in pinctrl_reg()
782 	pctl_desc->name = "eqbr-pinctrl";  in pinctrl_reg()
783 	pctl_desc->owner = THIS_MODULE;  in pinctrl_reg()
784 	pctl_desc->pctlops = &eqbr_pctl_ops;  in pinctrl_reg()
785 	pctl_desc->pmxops = &eqbr_pinmux_ops;  in pinctrl_reg()
786 	pctl_desc->confops = &eqbr_pinconf_ops;  in pinctrl_reg()
787 	raw_spin_lock_init(&drvdata->lock);  in pinctrl_reg()
789 	for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++)  in pinctrl_reg()
790 		nr_pins += drvdata->pin_banks[i].nr_pins;  in pinctrl_reg()
794 		return -ENOMEM;  in pinctrl_reg()
797 		return -ENOMEM;  in pinctrl_reg()
805 	pctl_desc->pins = pdesc;  in pinctrl_reg()
806 	pctl_desc->npins = nr_pins;  in pinctrl_reg()
810 					     &drvdata->pctl_dev);  in pinctrl_reg()
826 	return pinctrl_enable(drvdata->pctl_dev);  in pinctrl_reg()
831 			struct eqbr_pin_bank *bank, unsigned int id)  in pinbank_init()  argument
833 	struct device *dev = drvdata->dev;  in pinbank_init()
837 	bank->membase = drvdata->membase + id * PAD_REG_OFF;  in pinbank_init()
839 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec);  in pinbank_init()
841 		dev_err(dev, "gpio-range not available!\n");  in pinbank_init()
845 	bank->pin_base = spec.args[1];  in pinbank_init()
846 	bank->nr_pins = spec.args[2];  in pinbank_init()
848 	bank->aval_pinmap = readl(bank->membase + REG_AVAIL);  in pinbank_init()
849 	bank->id = id;  in pinbank_init()
851 	dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n",  in pinbank_init()
852 		id, bank->membase, bank->pin_base,  in pinbank_init()
853 		bank->nr_pins, bank->aval_pinmap);  in pinbank_init()
860 	struct device *dev = drvdata->dev;  in pinbank_probe()
875 		return -ENODEV;  in pinbank_probe()
881 		return -ENOMEM;  in pinbank_probe()
885 		return -ENOMEM;  in pinbank_probe()
902 	drvdata->pin_banks = banks;  in pinbank_probe()
903 	drvdata->nr_banks = nr_gpio;  in pinbank_probe()
904 	drvdata->gpio_ctrls = gctrls;  in pinbank_probe()
905 	drvdata->nr_gpio_ctrls = nr_gpio;  in pinbank_probe()
913 	struct device *dev = &pdev->dev;  in eqbr_pinctrl_probe()
918 		return -ENOMEM;  in eqbr_pinctrl_probe()
920 	drvdata->dev = dev;  in eqbr_pinctrl_probe()
922 	drvdata->membase = devm_platform_ioremap_resource(pdev, 0);  in eqbr_pinctrl_probe()
923 	if (IS_ERR(drvdata->membase))  in eqbr_pinctrl_probe()
924 		return PTR_ERR(drvdata->membase);  in eqbr_pinctrl_probe()
943 	{ .compatible = "intel,lgm-io" },
951 		.name = "eqbr-pinctrl",