1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
16 #include <linux/pinctrl/pinconf-generic.h>
45 #define NPCM7XX_GP_N_OE		0x10 /* Output Enable */
48 #define NPCM7XX_GP_N_PU		0x1c /* Pull-up */
49 #define NPCM7XX_GP_N_PD		0x20 /* Pull-down */
57 #define NPCM7XX_GP_N_EVEN	0x40 /* Event Enable */
58 #define NPCM7XX_GP_N_EVENS	0x44 /* Event Set (enable) */
63 #define NPCM7XX_GP_N_IEM	0x58 /* Input Enable */
68 #define NPCM7XX_GP_N_OES	0x70 /* Output Enable Set */
69 #define NPCM7XX_GP_N_OEC	0x74 /* Output Enable Clear */
108 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in npcm_gpio_set()
113 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in npcm_gpio_set()
122 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in npcm_gpio_clr()
127 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in npcm_gpio_clr()
134 	seq_printf(s, "-- module %d [gpio%d - %d]\n",  in npcmgpio_dbg_show()
135 		   bank->gc.base / bank->gc.ngpio,  in npcmgpio_dbg_show()
136 		   bank->gc.base,  in npcmgpio_dbg_show()
137 		   bank->gc.base + bank->gc.ngpio);  in npcmgpio_dbg_show()
139 		   ioread32(bank->base + NPCM7XX_GP_N_DIN),  in npcmgpio_dbg_show()
140 		   ioread32(bank->base + NPCM7XX_GP_N_DOUT),  in npcmgpio_dbg_show()
141 		   ioread32(bank->base + NPCM7XX_GP_N_IEM),  in npcmgpio_dbg_show()
142 		   ioread32(bank->base + NPCM7XX_GP_N_OE));  in npcmgpio_dbg_show()
144 		   ioread32(bank->base + NPCM7XX_GP_N_PU),  in npcmgpio_dbg_show()
145 		   ioread32(bank->base + NPCM7XX_GP_N_PD),  in npcmgpio_dbg_show()
146 		   ioread32(bank->base + NPCM7XX_GP_N_DBNC),  in npcmgpio_dbg_show()
147 		   ioread32(bank->base + NPCM7XX_GP_N_POL));  in npcmgpio_dbg_show()
149 		   ioread32(bank->base + NPCM7XX_GP_N_EVTYP),  in npcmgpio_dbg_show()
150 		   ioread32(bank->base + NPCM7XX_GP_N_EVBE),  in npcmgpio_dbg_show()
151 		   ioread32(bank->base + NPCM7XX_GP_N_EVEN),  in npcmgpio_dbg_show()
152 		   ioread32(bank->base + NPCM7XX_GP_N_EVST));  in npcmgpio_dbg_show()
154 		   ioread32(bank->base + NPCM7XX_GP_N_OTYP),  in npcmgpio_dbg_show()
155 		   ioread32(bank->base + NPCM7XX_GP_N_OSRC),  in npcmgpio_dbg_show()
156 		   ioread32(bank->base + NPCM7XX_GP_N_ODSC));  in npcmgpio_dbg_show()
158 		   ioread32(bank->base + NPCM7XX_GP_N_OBL0),  in npcmgpio_dbg_show()
159 		   ioread32(bank->base + NPCM7XX_GP_N_OBL1),  in npcmgpio_dbg_show()
160 		   ioread32(bank->base + NPCM7XX_GP_N_OBL2),  in npcmgpio_dbg_show()
161 		   ioread32(bank->base + NPCM7XX_GP_N_OBL3));  in npcmgpio_dbg_show()
163 		   ioread32(bank->base + NPCM7XX_GP_N_SPLCK),  in npcmgpio_dbg_show()
164 		   ioread32(bank->base + NPCM7XX_GP_N_MPLCK));  in npcmgpio_dbg_show()
172 	ret = pinctrl_gpio_direction_input(offset + chip->base);  in npcmgpio_direction_input()
176 	return bank->direction_input(chip, offset);  in npcmgpio_direction_input()
186 	dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset,  in npcmgpio_direction_output()
189 	ret = pinctrl_gpio_direction_output(offset + chip->base);  in npcmgpio_direction_output()
193 	return bank->direction_output(chip, offset, value);  in npcmgpio_direction_output()
201 	dev_dbg(chip->parent, "gpio_request: offset%d\n", offset);  in npcmgpio_gpio_request()
202 	ret = pinctrl_gpio_request(offset + chip->base);  in npcmgpio_gpio_request()
206 	return bank->request(chip, offset);  in npcmgpio_gpio_request()
211 	dev_dbg(chip->parent, "gpio_free: offset%d\n", offset);  in npcmgpio_gpio_free()
212 	pinctrl_gpio_free(offset + chip->base);  in npcmgpio_gpio_free()
227 	sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);  in npcmgpio_irq_handler()
228 	en  = ioread32(bank->base + NPCM7XX_GP_N_EVEN);  in npcmgpio_irq_handler()
229 	dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts,  in npcmgpio_irq_handler()
234 		generic_handle_domain_irq(gc->irq.domain, bit);  in npcmgpio_irq_handler()
242 	unsigned int gpio = BIT(d->hwirq);  in npcmgpio_set_irq_type()
244 	dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio,  in npcmgpio_set_irq_type()
245 		d->irq, type);  in npcmgpio_set_irq_type()
248 		dev_dbg(bank->gc.parent, "edge.rising\n");  in npcmgpio_set_irq_type()
249 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);  in npcmgpio_set_irq_type()
250 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);  in npcmgpio_set_irq_type()
253 		dev_dbg(bank->gc.parent, "edge.falling\n");  in npcmgpio_set_irq_type()
254 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);  in npcmgpio_set_irq_type()
255 		npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);  in npcmgpio_set_irq_type()
258 		dev_dbg(bank->gc.parent, "edge.both\n");  in npcmgpio_set_irq_type()
259 		npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);  in npcmgpio_set_irq_type()
262 		dev_dbg(bank->gc.parent, "level.low\n");  in npcmgpio_set_irq_type()
263 		npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);  in npcmgpio_set_irq_type()
266 		dev_dbg(bank->gc.parent, "level.high\n");  in npcmgpio_set_irq_type()
267 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);  in npcmgpio_set_irq_type()
270 		dev_dbg(bank->gc.parent, "invalid irq type\n");  in npcmgpio_set_irq_type()
271 		return -EINVAL;  in npcmgpio_set_irq_type()
275 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);  in npcmgpio_set_irq_type()
279 		npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);  in npcmgpio_set_irq_type()
290 	unsigned int gpio = d->hwirq;  in npcmgpio_irq_ack()
292 	dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq);  in npcmgpio_irq_ack()
293 	iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);  in npcmgpio_irq_ack()
301 	unsigned int gpio = d->hwirq;  in npcmgpio_irq_mask()
304 	dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq);  in npcmgpio_irq_mask()
305 	iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);  in npcmgpio_irq_mask()
308 /* Enable GPIO interrupt */
313 	unsigned int gpio = d->hwirq;  in npcmgpio_irq_unmask()
315 	/* Enable events */  in npcmgpio_irq_unmask()
316 	dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq);  in npcmgpio_irq_unmask()
317 	iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);  in npcmgpio_irq_unmask()
323 	unsigned int gpio = d->hwirq;  in npcmgpio_irq_startup()
325 	/* active-high, input, clear interrupt, enable interrupt */  in npcmgpio_irq_startup()
326 	dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq);  in npcmgpio_irq_startup()
335 	.name = "NPCM7XX-GPIO-IRQ",
915 #define SLEW		0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */  macro
916 #define SLEWLPC		0x8 /* Has Slew Control, SRCNT.3 */
931 	NPCM7XX_PINCFG(4,	 iox2, MFSEL3, 14,	 smb1d, I2CSEGSEL, 7,	none, NONE, 0,	     SLEW),
932 	NPCM7XX_PINCFG(5,	 iox2, MFSEL3, 14,	 smb1d, I2CSEGSEL, 7,	none, NONE, 0,	     SLEW),
933 	NPCM7XX_PINCFG(6,	 iox2, MFSEL3, 14,	 smb2d, I2CSEGSEL, 10,  none, NONE, 0,       SLEW),
934 	NPCM7XX_PINCFG(7,	 iox2, MFSEL3, 14,	 smb2d, I2CSEGSEL, 10,  none, NONE, 0,       SLEW),
939 	NPCM7XX_PINCFG(12,	 gspi, MFSEL1, 24,	 smb5b, I2CSEGSEL, 19,  none, NONE, 0,	     SLEW),
940 	NPCM7XX_PINCFG(13,	 gspi, MFSEL1, 24,	 smb5b, I2CSEGSEL, 19,  none, NONE, 0,	     SLEW),
941 	NPCM7XX_PINCFG(14,	 gspi, MFSEL1, 24,	 smb5c, I2CSEGSEL, 20,	none, NONE, 0,	     SLEW),
942 	NPCM7XX_PINCFG(15,	 gspi, MFSEL1, 24,	 smb5c, I2CSEGSEL, 20,	none, NONE, 0,	     SLEW),
961 	NPCM7XX_PINCFG(33,	 none, NONE, 0,           none, NONE, 0,	none, NONE, 0,	     SLEW),
962 	NPCM7XX_PINCFG(34,	 none, NONE, 0,           none, NONE, 0,	none, NONE, 0,	     SLEW),
963 	NPCM7XX_PINCFG(37,	smb3c, I2CSEGSEL, 12,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
964 	NPCM7XX_PINCFG(38,	smb3c, I2CSEGSEL, 12,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
965 	NPCM7XX_PINCFG(39,	smb3b, I2CSEGSEL, 11,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
966 	NPCM7XX_PINCFG(40,	smb3b, I2CSEGSEL, 11,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
1011 …G(84,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,	     DSTR(8, 12) | SLEW),
1012 …G(85,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,	     DSTR(8, 12) | SLEW),
1013 …G(86,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,	     DSTR(8, 12) | SLEW),
1048 	NPCM7XX_PINCFG(120,	smb2c, I2CSEGSEL, 9,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
1049 	NPCM7XX_PINCFG(121,	smb2c, I2CSEGSEL, 9,      none, NONE, 0,	none, NONE, 0,	     SLEW),
1050 	NPCM7XX_PINCFG(122,	smb2b, I2CSEGSEL, 8,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
1051 	NPCM7XX_PINCFG(123,	smb2b, I2CSEGSEL, 8,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
1052 	NPCM7XX_PINCFG(124,	smb1c, I2CSEGSEL, 6,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
1053 	NPCM7XX_PINCFG(125,	smb1c, I2CSEGSEL, 6,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
1054 	NPCM7XX_PINCFG(126,	smb1b, I2CSEGSEL, 5,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
1055 	NPCM7XX_PINCFG(127,	smb1b, I2CSEGSEL, 5,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
1065 	NPCM7XX_PINCFG(136,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1066 	NPCM7XX_PINCFG(137,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1067 	NPCM7XX_PINCFG(138,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1068 	NPCM7XX_PINCFG(139,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1069 	NPCM7XX_PINCFG(140,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1071 	NPCM7XX_PINCFG(142,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1077 	NPCM7XX_PINCFG(148,	 mmc8, MFSEL3, 11,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1078 	NPCM7XX_PINCFG(149,	 mmc8, MFSEL3, 11,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1079 	NPCM7XX_PINCFG(150,	 mmc8, MFSEL3, 11,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1080 	NPCM7XX_PINCFG(151,	 mmc8, MFSEL3, 11,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1081 	NPCM7XX_PINCFG(152,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1083 	NPCM7XX_PINCFG(154,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1085 	NPCM7XX_PINCFG(156,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1086 	NPCM7XX_PINCFG(157,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1087 	NPCM7XX_PINCFG(158,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1088 	NPCM7XX_PINCFG(159,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1090 …G(160,    clkout, MFSEL1, 21,        none, NONE, 0,        none, NONE, 0,	     DSTR(8, 12) | SLEW),
1108 	NPCM7XX_PINCFG(178,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1109 	NPCM7XX_PINCFG(179,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1110 	NPCM7XX_PINCFG(180,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1113 	NPCM7XX_PINCFG(183,     spi3, MFSEL4, 16,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1114 …NPCM7XX_PINCFG(184,     spi3, MFSEL4, 16,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW …
1115 …NPCM7XX_PINCFG(185,     spi3, MFSEL4, 16,	  none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW …
1118 …CFG(188,  spi3quad, MFSEL4, 20,     spi3cs2, MFSEL4, 18,     none, NONE, 0,    DSTR(8, 12) | SLEW),
1119 …CFG(189,  spi3quad, MFSEL4, 20,     spi3cs3, MFSEL4, 19,     none, NONE, 0,    DSTR(8, 12) | SLEW),
1128 	NPCM7XX_PINCFG(197,   smb0den, I2CSEGSEL, 22,     none, NONE, 0,	none, NONE, 0,	     SLEW),
1135 	NPCM7XX_PINCFG(204,	  ddc, NONE, 0,           gpio, MFSEL3, 22,	none, NONE, 0,	     SLEW),
1136 	NPCM7XX_PINCFG(205,	  ddc, NONE, 0,           gpio, MFSEL3, 22,	none, NONE, 0,	     SLEW),
1156 	NPCM7XX_PINCFG(224,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     SLEW),
1157 …PINCFG(225,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW | GPO),
1158 …PINCFG(226,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW | GPO),
1159 …CM7XX_PINCFG(227,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1160 …X_PINCFG(228,   spixcs1, MFSEL4, 28,        none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1161 …CM7XX_PINCFG(229,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1162 …CM7XX_PINCFG(230,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DSTR(8, 12) | SLEW),
1411 /* Enable mode in pin group */
1420 		if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {  in npcm7xx_setfunc()
1421 			if (cfg->reg0)  in npcm7xx_setfunc()
1422 				regmap_update_bits(gcr_regmap, cfg->reg0,  in npcm7xx_setfunc()
1423 						   BIT(cfg->bit0),  in npcm7xx_setfunc()
1424 						   !!(cfg->fn0 == mode) ?  in npcm7xx_setfunc()
1425 						   BIT(cfg->bit0) : 0);  in npcm7xx_setfunc()
1426 			if (cfg->reg1)  in npcm7xx_setfunc()
1427 				regmap_update_bits(gcr_regmap, cfg->reg1,  in npcm7xx_setfunc()
1428 						   BIT(cfg->bit1),  in npcm7xx_setfunc()
1429 						   !!(cfg->fn1 == mode) ?  in npcm7xx_setfunc()
1430 						   BIT(cfg->bit1) : 0);  in npcm7xx_setfunc()
1431 			if (cfg->reg2)  in npcm7xx_setfunc()
1432 				regmap_update_bits(gcr_regmap, cfg->reg2,  in npcm7xx_setfunc()
1433 						   BIT(cfg->bit2),  in npcm7xx_setfunc()
1434 						   !!(cfg->fn2 == mode) ?  in npcm7xx_setfunc()
1435 						   BIT(cfg->bit2) : 0);  in npcm7xx_setfunc()
1440 /* Get slew rate of pin (high/low) */
1445 	int gpio = (pin % bank->gc.ngpio);  in npcm7xx_get_slew_rate()
1448 	if (pincfg[pin].flag & SLEW)  in npcm7xx_get_slew_rate()
1449 		return ioread32(bank->base + NPCM7XX_GP_N_OSRC)  in npcm7xx_get_slew_rate()
1451 	/* LPC Slew rate in SRCNT register */  in npcm7xx_get_slew_rate()
1457 	return -EINVAL;  in npcm7xx_get_slew_rate()
1460 /* Set slew rate of pin (high/low) */
1465 	int gpio = BIT(pin % bank->gc.ngpio);  in npcm7xx_set_slew_rate()
1467 	if (pincfg[pin].flag & SLEW) {  in npcm7xx_set_slew_rate()
1470 			npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,  in npcm7xx_set_slew_rate()
1474 			npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,  in npcm7xx_set_slew_rate()
1478 			return -EINVAL;  in npcm7xx_set_slew_rate()
1481 	/* LPC Slew rate in SRCNT register */  in npcm7xx_set_slew_rate()
1493 			return -EINVAL;  in npcm7xx_set_slew_rate()
1497 	return -EINVAL;  in npcm7xx_set_slew_rate()
1506 		&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];  in npcm7xx_get_drive_strength()
1507 	int gpio = (pin % bank->gc.ngpio);  in npcm7xx_get_drive_strength()
1515 		val = ioread32(bank->base + NPCM7XX_GP_N_ODSC)  in npcm7xx_get_drive_strength()
1518 		dev_dbg(bank->gc.parent,  in npcm7xx_get_drive_strength()
1523 	return -EINVAL;  in npcm7xx_get_drive_strength()
1532 		&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];  in npcm7xx_set_drive_strength()
1533 	int gpio = BIT(pin % bank->gc.ngpio);  in npcm7xx_set_drive_strength()
1537 		return -ENOTSUPP;  in npcm7xx_set_drive_strength()
1539 		dev_dbg(bank->gc.parent,  in npcm7xx_set_drive_strength()
1541 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);  in npcm7xx_set_drive_strength()
1544 		dev_dbg(bank->gc.parent,  in npcm7xx_set_drive_strength()
1546 		npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);  in npcm7xx_set_drive_strength()
1550 	return -ENOTSUPP;  in npcm7xx_set_drive_strength()
1564 	dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups));  in npcm7xx_get_groups_count()
1592 	dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name);  in npcm7xx_dt_node_to_map()
1642 	dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group,  in npcm7xx_pinmux_set_mux()
1645 	npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins,  in npcm7xx_pinmux_set_mux()
1658 		dev_err(npcm->dev, "invalid range\n");  in npcm7xx_gpio_request_enable()
1659 		return -EINVAL;  in npcm7xx_gpio_request_enable()
1661 	if (!range->gc) {  in npcm7xx_gpio_request_enable()
1662 		dev_err(npcm->dev, "invalid gpiochip\n");  in npcm7xx_gpio_request_enable()
1663 		return -EINVAL;  in npcm7xx_gpio_request_enable()
1666 	npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio);  in npcm7xx_gpio_request_enable()
1679 	virq = irq_find_mapping(npcm->domain, offset);  in npcm7xx_gpio_request_free()
1691 		&npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK];  in npcm_gpio_set_direction()
1692 	int gpio = BIT(offset % bank->gc.ngpio);  in npcm_gpio_set_direction()
1694 	dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset,  in npcm_gpio_set_direction()
1697 		iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);  in npcm_gpio_set_direction()
1699 		iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);  in npcm_gpio_set_direction()
1721 		&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];  in npcm7xx_config_get()
1722 	int gpio = (pin % bank->gc.ngpio);  in npcm7xx_config_get()
1731 		pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask;  in npcm7xx_config_get()
1732 		pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask;  in npcm7xx_config_get()
1742 		ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;  in npcm7xx_config_get()
1743 		oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;  in npcm7xx_config_get()
1750 		rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask);  in npcm7xx_config_get()
1753 		rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask;  in npcm7xx_config_get()
1756 		rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask;  in npcm7xx_config_get()
1764 		rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin);  in npcm7xx_config_get()
1769 		return -ENOTSUPP;  in npcm7xx_config_get()
1773 		return -EINVAL;  in npcm7xx_config_get()
1784 		&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];  in npcm7xx_config_set_one()
1785 	int gpio = BIT(pin % bank->gc.ngpio);  in npcm7xx_config_set_one()
1787 	dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin);  in npcm7xx_config_set_one()
1790 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);  in npcm7xx_config_set_one()
1791 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);  in npcm7xx_config_set_one()
1794 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);  in npcm7xx_config_set_one()
1795 		npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);  in npcm7xx_config_set_one()
1798 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);  in npcm7xx_config_set_one()
1799 		npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);  in npcm7xx_config_set_one()
1802 		iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);  in npcm7xx_config_set_one()
1803 		bank->direction_input(&bank->gc, pin % bank->gc.ngpio);  in npcm7xx_config_set_one()
1806 		iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);  in npcm7xx_config_set_one()
1807 		bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);  in npcm7xx_config_set_one()
1810 		npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);  in npcm7xx_config_set_one()
1813 		npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);  in npcm7xx_config_set_one()
1816 		npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio);  in npcm7xx_config_set_one()
1819 		return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);  in npcm7xx_config_set_one()
1823 		return -ENOTSUPP;  in npcm7xx_config_set_one()
1836 	while (num_configs--) {  in npcm7xx_config_set()
1853 	.name = "npcm7xx-pinctrl",
1864 	int ret = -ENXIO;  in npcm7xx_gpio_of()
1866 	struct device *dev = pctrl->dev;  in npcm7xx_gpio_of()
1880 		pctrl->gpio_bank[id].base = ioremap(res.start, resource_size(&res));  in npcm7xx_gpio_of()
1882 		ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,  in npcm7xx_gpio_of()
1883 				 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN,  in npcm7xx_gpio_of()
1884 				 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT,  in npcm7xx_gpio_of()
1887 				 pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM,  in npcm7xx_gpio_of()
1894 		ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);  in npcm7xx_gpio_of()
1896 			dev_err(dev, "gpio-ranges fail for GPIO bank %u\n", id);  in npcm7xx_gpio_of()
1903 			return -EINVAL;  in npcm7xx_gpio_of()
1905 		pctrl->gpio_bank[id].irq = ret;  in npcm7xx_gpio_of()
1906 		pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;  in npcm7xx_gpio_of()
1907 		pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK;  in npcm7xx_gpio_of()
1908 		pctrl->gpio_bank[id].pinctrl_id = args.args[0];  in npcm7xx_gpio_of()
1909 		pctrl->gpio_bank[id].gc.base = args.args[1];  in npcm7xx_gpio_of()
1910 		pctrl->gpio_bank[id].gc.ngpio = args.args[2];  in npcm7xx_gpio_of()
1911 		pctrl->gpio_bank[id].gc.owner = THIS_MODULE;  in npcm7xx_gpio_of()
1912 		pctrl->gpio_bank[id].gc.parent = dev;  in npcm7xx_gpio_of()
1913 		pctrl->gpio_bank[id].gc.fwnode = child;  in npcm7xx_gpio_of()
1914 		pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);  in npcm7xx_gpio_of()
1915 		if (pctrl->gpio_bank[id].gc.label == NULL)  in npcm7xx_gpio_of()
1916 			return -ENOMEM;  in npcm7xx_gpio_of()
1918 		pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;  in npcm7xx_gpio_of()
1919 		pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input;  in npcm7xx_gpio_of()
1920 		pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input;  in npcm7xx_gpio_of()
1921 		pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output;  in npcm7xx_gpio_of()
1922 		pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;  in npcm7xx_gpio_of()
1923 		pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;  in npcm7xx_gpio_of()
1924 		pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;  in npcm7xx_gpio_of()
1925 		pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;  in npcm7xx_gpio_of()
1929 	pctrl->bank_num = id;  in npcm7xx_gpio_of()
1937 	for (id = 0 ; id < pctrl->bank_num ; id++) {  in npcm7xx_gpio_register()
1940 		girq = &pctrl->gpio_bank[id].gc.irq;  in npcm7xx_gpio_register()
1941 		girq->chip = &pctrl->gpio_bank[id].irq_chip;  in npcm7xx_gpio_register()
1942 		girq->parent_handler = npcmgpio_irq_handler;  in npcm7xx_gpio_register()
1943 		girq->num_parents = 1;  in npcm7xx_gpio_register()
1944 		girq->parents = devm_kcalloc(pctrl->dev, 1,  in npcm7xx_gpio_register()
1945 					     sizeof(*girq->parents),  in npcm7xx_gpio_register()
1947 		if (!girq->parents) {  in npcm7xx_gpio_register()
1948 			ret = -ENOMEM;  in npcm7xx_gpio_register()
1951 		girq->parents[0] = pctrl->gpio_bank[id].irq;  in npcm7xx_gpio_register()
1952 		girq->default_type = IRQ_TYPE_NONE;  in npcm7xx_gpio_register()
1953 		girq->handler = handle_level_irq;  in npcm7xx_gpio_register()
1954 		ret = devm_gpiochip_add_data(pctrl->dev,  in npcm7xx_gpio_register()
1955 					     &pctrl->gpio_bank[id].gc,  in npcm7xx_gpio_register()
1956 					     &pctrl->gpio_bank[id]);  in npcm7xx_gpio_register()
1958 			dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id);  in npcm7xx_gpio_register()
1962 		ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc,  in npcm7xx_gpio_register()
1963 					     dev_name(pctrl->dev),  in npcm7xx_gpio_register()
1964 					     pctrl->gpio_bank[id].pinctrl_id,  in npcm7xx_gpio_register()
1965 					     pctrl->gpio_bank[id].gc.base,  in npcm7xx_gpio_register()
1966 					     pctrl->gpio_bank[id].gc.ngpio);  in npcm7xx_gpio_register()
1968 			dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id);  in npcm7xx_gpio_register()
1969 			gpiochip_remove(&pctrl->gpio_bank[id].gc);  in npcm7xx_gpio_register()
1977 	for (; id > 0; id--)  in npcm7xx_gpio_register()
1978 		gpiochip_remove(&pctrl->gpio_bank[id - 1].gc);  in npcm7xx_gpio_register()
1988 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);  in npcm7xx_pinctrl_probe()
1990 		return -ENOMEM;  in npcm7xx_pinctrl_probe()
1992 	pctrl->dev = &pdev->dev;  in npcm7xx_pinctrl_probe()
1993 	dev_set_drvdata(&pdev->dev, pctrl);  in npcm7xx_pinctrl_probe()
1995 	pctrl->gcr_regmap =  in npcm7xx_pinctrl_probe()
1996 		syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");  in npcm7xx_pinctrl_probe()
1997 	if (IS_ERR(pctrl->gcr_regmap)) {  in npcm7xx_pinctrl_probe()
1998 		dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n");  in npcm7xx_pinctrl_probe()
1999 		return PTR_ERR(pctrl->gcr_regmap);  in npcm7xx_pinctrl_probe()
2004 		dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret);  in npcm7xx_pinctrl_probe()
2008 	pctrl->pctldev = devm_pinctrl_register(&pdev->dev,  in npcm7xx_pinctrl_probe()
2010 	if (IS_ERR(pctrl->pctldev)) {  in npcm7xx_pinctrl_probe()
2011 		dev_err(&pdev->dev, "Failed to register pinctrl device\n");  in npcm7xx_pinctrl_probe()
2012 		return PTR_ERR(pctrl->pctldev);  in npcm7xx_pinctrl_probe()
2017 		dev_err(pctrl->dev, "Failed to register gpio %u\n", ret);  in npcm7xx_pinctrl_probe()
2026 	{ .compatible = "nuvoton,npcm750-pinctrl" },
2034 		.name = "npcm7xx-pinctrl",