Lines Matching +full:0 +full:x60
18 #define DRV_BASE1 0x500
19 #define DRV_BASE2 0x510
20 #define PUPD_BASE1 0x400
21 #define PUPD_BASE2 0x450
22 #define R0_BASE1 0x4d0
23 #define R1_BASE1 0x200
24 #define R1_BASE2 0x250
50 MTK_DRV_GRP(2, 16, 0, 2, 2),
54 MTK_DRV_GRP(2, 8, 0, 1, 2),
56 MTK_DRV_GRP(4, 32, 0, 2, 4)
60 MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
61 MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
62 MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
63 MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
64 MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
65 MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
66 MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
67 MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
68 MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
69 MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
100 MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
101 MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
102 MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
103 MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
104 MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
105 MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
106 MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
107 MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),
109 MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
110 MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
111 MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
112 MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
113 MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
114 MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
115 MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),
116 MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),
117 MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),
118 MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),
119 MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),
120 MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),
121 MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),
123 MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),
124 MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),
125 MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),
126 MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),
127 MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),
128 MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),
129 MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),
130 MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),
131 MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),
133 MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),
134 MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),
136 MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),
137 MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),
139 MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),
140 MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),
141 MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),
142 MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),
143 MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),
144 MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),
146 MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
147 MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
148 MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
149 MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
150 MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
151 MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
152 MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
154 MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),
156 MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
157 MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
158 MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),
159 MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),
160 MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),
163 MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),
164 MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),
165 MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),
166 MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),
167 MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),
168 MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),
169 MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),
170 MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),
171 MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),
172 MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),
173 MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),
175 MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),
176 MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),
177 MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),
178 MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),
179 MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),
180 MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),
182 MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),
183 MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),
184 MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),
185 MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),
186 MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),
188 MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),
189 MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),
190 MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),
191 MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),
192 MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),
193 MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),
194 MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),
196 MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),
197 MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),
198 MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),
199 MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),
200 MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),
201 MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)
205 SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0),
210 SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5),
222 SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0),
223 SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1),
224 SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2),
225 SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5),
226 SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6),
227 SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7),
228 SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8),
229 SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9),
230 SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
243 for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) { in spec_pull_set()
286 return 0; in spec_pull_set()
297 .dir_offset = 0x0000,
298 .ies_offset = 0x0100,
299 .pullen_offset = 0x0200,
300 .smt_offset = 0x0300,
301 .pullsel_offset = 0x0400,
302 .dout_offset = 0x0800,
303 .din_offset = 0x0A00,
304 .pinmux_offset = 0x0C00,
308 .port_mask = 0xf,
310 .mode_mask = 0xf,