Lines Matching +full:mux +full:- +full:locked
1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/pinctrl/pinconf-generic.h>
25 #include "pinctrl-intel.h"
98 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
99 #define padgroup_offset(g, p) ((p) - (g)->base)
107 for (i = 0; i < pctrl->ncommunities; i++) { in intel_get_community()
108 community = &pctrl->communities[i]; in intel_get_community()
109 if (pin >= community->pin_base && in intel_get_community()
110 pin < community->pin_base + community->npins) in intel_get_community()
114 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); in intel_get_community()
124 for (i = 0; i < community->ngpps; i++) { in intel_community_get_padgroup()
125 const struct intel_padgroup *padgrp = &community->gpps[i]; in intel_community_get_padgroup()
127 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) in intel_community_get_padgroup()
146 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; in intel_get_padcfg()
151 return community->pad_regs + reg + padno * nregs * 4; in intel_get_padcfg()
164 if (!community->padown_offset) in intel_pad_owned_by_host()
173 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; in intel_pad_owned_by_host()
174 padown = community->regs + offset; in intel_pad_owned_by_host()
189 if (!community->hostown_offset) in intel_pad_acpi_mode()
197 offset = community->hostown_offset + padgrp->reg_num * 4; in intel_pad_acpi_mode()
198 hostown = community->regs + offset; in intel_pad_acpi_mode()
204 * enum - Locking variants of the pad configuration
207 * @PAD_LOCKED: pad configuration registers, except TX state, are locked
208 * @PAD_LOCKED_TX: pad configuration TX state is locked
209 * @PAD_LOCKED_FULL: pad configuration registers are locked completely
211 * Locking is considered as read-only mode for corresponding registers and
212 * their respective fields. That said, TX state bit is locked separately from
233 if (!community->padcfglock_offset) in intel_pad_locked()
245 * either fully or partially locked. in intel_pad_locked()
247 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; in intel_pad_locked()
248 value = readl(community->regs + offset); in intel_pad_locked()
252 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; in intel_pad_locked()
253 value = readl(community->regs + offset); in intel_pad_locked()
274 return pctrl->soc->ngroups; in intel_get_groups_count()
282 return pctrl->soc->groups[group].grp.name; in intel_get_group_name()
290 *pins = pctrl->soc->groups[group].grp.pins; in intel_get_group_pins()
291 *npins = pctrl->soc->groups[group].grp.npins; in intel_get_group_pins()
301 int locked; in intel_pin_dbg_show() local
325 locked = intel_pad_locked(pctrl, pin); in intel_pin_dbg_show()
328 if (locked || acpi) { in intel_pin_dbg_show()
330 if (locked) in intel_pin_dbg_show()
331 seq_puts(s, "LOCKED"); in intel_pin_dbg_show()
332 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) in intel_pin_dbg_show()
334 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) in intel_pin_dbg_show()
337 if (locked && acpi) in intel_pin_dbg_show()
357 return pctrl->soc->nfunctions; in intel_get_functions_count()
365 return pctrl->soc->functions[function].name; in intel_get_function_name()
375 *groups = pctrl->soc->functions[function].groups; in intel_get_function_groups()
376 *ngroups = pctrl->soc->functions[function].ngroups; in intel_get_function_groups()
384 const struct intel_pingroup *grp = &pctrl->soc->groups[group]; in intel_pinmux_set_mux()
388 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_pinmux_set_mux()
392 * before we can enable the mux for this group. in intel_pinmux_set_mux()
394 for (i = 0; i < grp->grp.npins; i++) { in intel_pinmux_set_mux()
395 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) { in intel_pinmux_set_mux()
396 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_pinmux_set_mux()
397 return -EBUSY; in intel_pinmux_set_mux()
401 /* Now enable the mux setting for each pin in the group */ in intel_pinmux_set_mux()
402 for (i = 0; i < grp->grp.npins; i++) { in intel_pinmux_set_mux()
406 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0); in intel_pinmux_set_mux()
411 if (grp->modes) in intel_pinmux_set_mux()
412 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; in intel_pinmux_set_mux()
414 value |= grp->mode << PADCFG0_PMODE_SHIFT; in intel_pinmux_set_mux()
419 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_pinmux_set_mux()
480 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_gpio_request_enable()
483 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_gpio_request_enable()
484 return -EBUSY; in intel_gpio_request_enable()
488 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_gpio_request_enable()
499 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_gpio_request_enable()
505 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_gpio_request_enable()
520 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_gpio_set_direction()
522 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_gpio_set_direction()
547 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_config_get_pull()
549 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_config_get_pull()
556 return -EINVAL; in intel_config_get_pull()
561 return -EINVAL; in intel_config_get_pull()
582 return -EINVAL; in intel_config_get_pull()
586 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_get_pull()
587 return -EINVAL; in intel_config_get_pull()
591 if (!(community->features & PINCTRL_FEATURE_1K_PD)) in intel_config_get_pull()
592 return -EINVAL; in intel_config_get_pull()
606 return -EINVAL; in intel_config_get_pull()
622 return -ENOTSUPP; in intel_config_get_debounce()
624 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_config_get_debounce()
626 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_config_get_debounce()
628 return -EINVAL; in intel_config_get_debounce()
645 return -ENOTSUPP; in intel_config_get()
663 return -ENOTSUPP; in intel_config_get()
684 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_config_set_pull()
716 ret = -EINVAL; in intel_config_set_pull()
736 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { in intel_config_set_pull()
737 ret = -EINVAL; in intel_config_set_pull()
743 if (!(community->features & PINCTRL_FEATURE_1K_PD)) { in intel_config_set_pull()
744 ret = -EINVAL; in intel_config_set_pull()
750 ret = -EINVAL; in intel_config_set_pull()
759 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_config_set_pull()
773 return -ENOTSUPP; in intel_config_set_debounce()
777 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_config_set_debounce()
791 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_config_set_debounce()
792 return -EINVAL; in intel_config_set_debounce()
804 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_config_set_debounce()
816 return -ENOTSUPP; in intel_config_set()
836 return -ENOTSUPP; in intel_config_set()
857 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
876 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_to_pin()
877 const struct intel_community *comm = &pctrl->communities[i]; in intel_gpio_to_pin()
880 for (j = 0; j < comm->ngpps; j++) { in intel_gpio_to_pin()
881 const struct intel_padgroup *pgrp = &comm->gpps[j]; in intel_gpio_to_pin()
883 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) in intel_gpio_to_pin()
886 if (offset >= pgrp->gpio_base && in intel_gpio_to_pin()
887 offset < pgrp->gpio_base + pgrp->size) { in intel_gpio_to_pin()
890 pin = pgrp->base + offset - pgrp->gpio_base; in intel_gpio_to_pin()
901 return -EINVAL; in intel_gpio_to_pin()
905 * intel_pin_to_gpio() - Translate from pin number to GPIO offset
920 return -EINVAL; in intel_pin_to_gpio()
924 return -EINVAL; in intel_pin_to_gpio()
926 return pin - padgrp->base + padgrp->gpio_base; in intel_pin_to_gpio()
938 return -EINVAL; in intel_gpio_get()
942 return -EINVAL; in intel_gpio_get()
968 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_gpio_set()
975 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_gpio_set()
988 return -EINVAL; in intel_gpio_get_direction()
992 return -EINVAL; in intel_gpio_get_direction()
994 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_gpio_get_direction()
996 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_gpio_get_direction()
998 return -EINVAL; in intel_gpio_get_direction()
1008 return pinctrl_gpio_direction_input(chip->base + offset); in intel_gpio_direction_input()
1015 return pinctrl_gpio_direction_output(chip->base + offset); in intel_gpio_direction_output()
1042 gpp = padgrp->reg_num; in intel_gpio_irq_ack()
1044 is_offset = community->is_offset + gpp * 4; in intel_gpio_irq_ack()
1046 raw_spin_lock(&pctrl->lock); in intel_gpio_irq_ack()
1047 writel(BIT(gpp_offset), community->regs + is_offset); in intel_gpio_irq_ack()
1048 raw_spin_unlock(&pctrl->lock); in intel_gpio_irq_ack()
1066 gpp = padgrp->reg_num; in intel_gpio_irq_mask_unmask()
1069 reg = community->regs + community->ie_offset + gpp * 4; in intel_gpio_irq_mask_unmask()
1070 is = community->regs + community->is_offset + gpp * 4; in intel_gpio_irq_mask_unmask()
1072 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_gpio_irq_mask_unmask()
1083 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_gpio_irq_mask_unmask()
1116 return -EINVAL; in intel_gpio_irq_type()
1124 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); in intel_gpio_irq_type()
1125 return -EPERM; in intel_gpio_irq_type()
1128 raw_spin_lock_irqsave(&pctrl->lock, flags); in intel_gpio_irq_type()
1157 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in intel_gpio_irq_type()
1169 enable_irq_wake(pctrl->irq); in intel_gpio_irq_wake()
1171 disable_irq_wake(pctrl->irq); in intel_gpio_irq_wake()
1173 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); in intel_gpio_irq_wake()
1178 .name = "intel-gpio",
1191 struct gpio_chip *gc = &pctrl->chip; in intel_gpio_community_irq_handler()
1195 for (gpp = 0; gpp < community->ngpps; gpp++) { in intel_gpio_community_irq_handler()
1196 const struct intel_padgroup *padgrp = &community->gpps[gpp]; in intel_gpio_community_irq_handler()
1199 raw_spin_lock(&pctrl->lock); in intel_gpio_community_irq_handler()
1201 pending = readl(community->regs + community->is_offset + in intel_gpio_community_irq_handler()
1202 padgrp->reg_num * 4); in intel_gpio_community_irq_handler()
1203 enabled = readl(community->regs + community->ie_offset + in intel_gpio_community_irq_handler()
1204 padgrp->reg_num * 4); in intel_gpio_community_irq_handler()
1206 raw_spin_unlock(&pctrl->lock); in intel_gpio_community_irq_handler()
1211 for_each_set_bit(gpp_offset, &pending, padgrp->size) { in intel_gpio_community_irq_handler()
1214 irq = irq_find_mapping(gc->irq.domain, in intel_gpio_community_irq_handler()
1215 padgrp->gpio_base + gpp_offset); in intel_gpio_community_irq_handler()
1233 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_irq()
1234 community = &pctrl->communities[i]; in intel_gpio_irq()
1245 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_irq_init()
1250 community = &pctrl->communities[i]; in intel_gpio_irq_init()
1251 base = community->regs; in intel_gpio_irq_init()
1253 for (gpp = 0; gpp < community->ngpps; gpp++) { in intel_gpio_irq_init()
1255 writel(0, base + community->ie_offset + gpp * 4); in intel_gpio_irq_init()
1256 writel(0xffff, base + community->is_offset + gpp * 4); in intel_gpio_irq_init()
1279 for (i = 0; i < community->ngpps; i++) { in intel_gpio_add_community_ranges()
1280 const struct intel_padgroup *gpp = &community->gpps[i]; in intel_gpio_add_community_ranges()
1282 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) in intel_gpio_add_community_ranges()
1285 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), in intel_gpio_add_community_ranges()
1286 gpp->gpio_base, gpp->base, in intel_gpio_add_community_ranges()
1287 gpp->size); in intel_gpio_add_community_ranges()
1300 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_add_pin_ranges()
1301 struct intel_community *community = &pctrl->communities[i]; in intel_gpio_add_pin_ranges()
1305 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); in intel_gpio_add_pin_ranges()
1319 for (i = 0; i < pctrl->ncommunities; i++) { in intel_gpio_ngpio()
1320 community = &pctrl->communities[i]; in intel_gpio_ngpio()
1321 for (j = 0; j < community->ngpps; j++) { in intel_gpio_ngpio()
1322 const struct intel_padgroup *gpp = &community->gpps[j]; in intel_gpio_ngpio()
1324 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) in intel_gpio_ngpio()
1327 if (gpp->gpio_base + gpp->size > ngpio) in intel_gpio_ngpio()
1328 ngpio = gpp->gpio_base + gpp->size; in intel_gpio_ngpio()
1340 pctrl->chip = intel_gpio_chip; in intel_gpio_probe()
1343 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); in intel_gpio_probe()
1344 pctrl->chip.label = dev_name(pctrl->dev); in intel_gpio_probe()
1345 pctrl->chip.parent = pctrl->dev; in intel_gpio_probe()
1346 pctrl->chip.base = -1; in intel_gpio_probe()
1347 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; in intel_gpio_probe()
1348 pctrl->irq = irq; in intel_gpio_probe()
1354 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, in intel_gpio_probe()
1356 dev_name(pctrl->dev), pctrl); in intel_gpio_probe()
1358 dev_err(pctrl->dev, "failed to request interrupt\n"); in intel_gpio_probe()
1363 girq = &pctrl->chip.irq; in intel_gpio_probe()
1366 girq->parent_handler = NULL; in intel_gpio_probe()
1367 girq->num_parents = 0; in intel_gpio_probe()
1368 girq->default_type = IRQ_TYPE_NONE; in intel_gpio_probe()
1369 girq->handler = handle_bad_irq; in intel_gpio_probe()
1370 girq->init_hw = intel_gpio_irq_init_hw; in intel_gpio_probe()
1372 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); in intel_gpio_probe()
1374 dev_err(pctrl->dev, "failed to register gpiochip\n"); in intel_gpio_probe()
1386 size_t i, ngpps = community->ngpps; in intel_pinctrl_add_padgroups_by_gpps()
1388 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); in intel_pinctrl_add_padgroups_by_gpps()
1390 return -ENOMEM; in intel_pinctrl_add_padgroups_by_gpps()
1393 gpps[i] = community->gpps[i]; in intel_pinctrl_add_padgroups_by_gpps()
1396 return -EINVAL; in intel_pinctrl_add_padgroups_by_gpps()
1416 community->gpps = gpps; in intel_pinctrl_add_padgroups_by_gpps()
1425 unsigned int npins = community->npins; in intel_pinctrl_add_padgroups_by_size()
1427 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); in intel_pinctrl_add_padgroups_by_size()
1429 if (community->gpp_size > 32) in intel_pinctrl_add_padgroups_by_size()
1430 return -EINVAL; in intel_pinctrl_add_padgroups_by_size()
1432 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); in intel_pinctrl_add_padgroups_by_size()
1434 return -ENOMEM; in intel_pinctrl_add_padgroups_by_size()
1437 unsigned int gpp_size = community->gpp_size; in intel_pinctrl_add_padgroups_by_size()
1440 gpps[i].base = community->pin_base + i * gpp_size; in intel_pinctrl_add_padgroups_by_size()
1442 npins -= gpps[i].size; in intel_pinctrl_add_padgroups_by_size()
1451 if (community->gpp_num_padown_regs) in intel_pinctrl_add_padgroups_by_size()
1452 padown_num += community->gpp_num_padown_regs; in intel_pinctrl_add_padgroups_by_size()
1457 community->ngpps = ngpps; in intel_pinctrl_add_padgroups_by_size()
1458 community->gpps = gpps; in intel_pinctrl_add_padgroups_by_size()
1466 const struct intel_pinctrl_soc_data *soc = pctrl->soc; in intel_pinctrl_pm_init()
1471 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); in intel_pinctrl_pm_init()
1473 return -ENOMEM; in intel_pinctrl_pm_init()
1475 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, in intel_pinctrl_pm_init()
1478 return -ENOMEM; in intel_pinctrl_pm_init()
1481 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_pm_init()
1482 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_pm_init()
1485 intmask = devm_kcalloc(pctrl->dev, community->ngpps, in intel_pinctrl_pm_init()
1488 return -ENOMEM; in intel_pinctrl_pm_init()
1492 hostown = devm_kcalloc(pctrl->dev, community->ngpps, in intel_pinctrl_pm_init()
1495 return -ENOMEM; in intel_pinctrl_pm_init()
1500 pctrl->context.pads = pads; in intel_pinctrl_pm_init()
1501 pctrl->context.communities = communities; in intel_pinctrl_pm_init()
1513 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in intel_pinctrl_probe()
1515 return -ENOMEM; in intel_pinctrl_probe()
1517 pctrl->dev = &pdev->dev; in intel_pinctrl_probe()
1518 pctrl->soc = soc_data; in intel_pinctrl_probe()
1519 raw_spin_lock_init(&pctrl->lock); in intel_pinctrl_probe()
1525 pctrl->ncommunities = pctrl->soc->ncommunities; in intel_pinctrl_probe()
1526 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, in intel_pinctrl_probe()
1527 sizeof(*pctrl->communities), GFP_KERNEL); in intel_pinctrl_probe()
1528 if (!pctrl->communities) in intel_pinctrl_probe()
1529 return -ENOMEM; in intel_pinctrl_probe()
1531 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_probe()
1532 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_probe()
1537 *community = pctrl->soc->communities[i]; in intel_pinctrl_probe()
1539 regs = devm_platform_ioremap_resource(pdev, community->barno); in intel_pinctrl_probe()
1549 return -ENODEV; in intel_pinctrl_probe()
1551 community->features |= PINCTRL_FEATURE_DEBOUNCE; in intel_pinctrl_probe()
1552 community->features |= PINCTRL_FEATURE_1K_PD; in intel_pinctrl_probe()
1561 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; in intel_pinctrl_probe()
1564 community->features |= PINCTRL_FEATURE_PWM; in intel_pinctrl_probe()
1567 community->features |= PINCTRL_FEATURE_BLINK; in intel_pinctrl_probe()
1570 community->features |= PINCTRL_FEATURE_EXP; in intel_pinctrl_probe()
1578 dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features); in intel_pinctrl_probe()
1583 community->regs = regs; in intel_pinctrl_probe()
1584 community->pad_regs = regs + offset; in intel_pinctrl_probe()
1586 if (community->gpps) in intel_pinctrl_probe()
1602 pctrl->pctldesc = intel_pinctrl_desc; in intel_pinctrl_probe()
1603 pctrl->pctldesc.name = dev_name(&pdev->dev); in intel_pinctrl_probe()
1604 pctrl->pctldesc.pins = pctrl->soc->pins; in intel_pinctrl_probe()
1605 pctrl->pctldesc.npins = pctrl->soc->npins; in intel_pinctrl_probe()
1607 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, in intel_pinctrl_probe()
1609 if (IS_ERR(pctrl->pctldev)) { in intel_pinctrl_probe()
1610 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); in intel_pinctrl_probe()
1611 return PTR_ERR(pctrl->pctldev); in intel_pinctrl_probe()
1627 data = device_get_match_data(&pdev->dev); in intel_pinctrl_probe_by_hid()
1629 return -ENODATA; in intel_pinctrl_probe_by_hid()
1652 table = device_get_match_data(&pdev->dev); in intel_pinctrl_get_soc_data()
1654 struct acpi_device *adev = ACPI_COMPANION(&pdev->dev); in intel_pinctrl_get_soc_data()
1658 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { in intel_pinctrl_get_soc_data()
1668 return ERR_PTR(-ENODEV); in intel_pinctrl_get_soc_data()
1670 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data; in intel_pinctrl_get_soc_data()
1671 data = table[pdev->id]; in intel_pinctrl_get_soc_data()
1674 return data ?: ERR_PTR(-ENODATA); in intel_pinctrl_get_soc_data()
1681 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); in intel_pinctrl_should_save()
1690 * BIOS during resume and those are not always locked down so leave in intel_pinctrl_should_save()
1693 if (pd->mux_owner || pd->gpio_owner || in intel_pinctrl_should_save()
1694 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) in intel_pinctrl_should_save()
1726 pads = pctrl->context.pads; in intel_pinctrl_suspend_noirq()
1727 for (i = 0; i < pctrl->soc->npins; i++) { in intel_pinctrl_suspend_noirq()
1728 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; in intel_pinctrl_suspend_noirq()
1732 if (!intel_pinctrl_should_save(pctrl, desc->number)) in intel_pinctrl_suspend_noirq()
1735 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); in intel_pinctrl_suspend_noirq()
1737 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); in intel_pinctrl_suspend_noirq()
1740 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); in intel_pinctrl_suspend_noirq()
1745 communities = pctrl->context.communities; in intel_pinctrl_suspend_noirq()
1746 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_suspend_noirq()
1747 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_suspend_noirq()
1751 base = community->regs + community->ie_offset; in intel_pinctrl_suspend_noirq()
1752 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_suspend_noirq()
1755 base = community->regs + community->hostown_offset; in intel_pinctrl_suspend_noirq()
1756 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_suspend_noirq()
1781 const struct intel_community *community = &pctrl->communities[c]; in intel_restore_hostown()
1782 const struct intel_padgroup *padgrp = &community->gpps[gpp]; in intel_restore_hostown()
1783 struct device *dev = pctrl->dev; in intel_restore_hostown()
1788 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) in intel_restore_hostown()
1791 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) in intel_restore_hostown()
1803 struct device *dev = pctrl->dev; in intel_restore_intmask()
1816 struct device *dev = pctrl->dev; in intel_restore_padcfg()
1839 pads = pctrl->context.pads; in intel_pinctrl_resume_noirq()
1840 for (i = 0; i < pctrl->soc->npins; i++) { in intel_pinctrl_resume_noirq()
1841 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; in intel_pinctrl_resume_noirq()
1843 if (!intel_pinctrl_should_save(pctrl, desc->number)) in intel_pinctrl_resume_noirq()
1846 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); in intel_pinctrl_resume_noirq()
1847 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); in intel_pinctrl_resume_noirq()
1848 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); in intel_pinctrl_resume_noirq()
1851 communities = pctrl->context.communities; in intel_pinctrl_resume_noirq()
1852 for (i = 0; i < pctrl->ncommunities; i++) { in intel_pinctrl_resume_noirq()
1853 struct intel_community *community = &pctrl->communities[i]; in intel_pinctrl_resume_noirq()
1857 base = community->regs + community->ie_offset; in intel_pinctrl_resume_noirq()
1858 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_resume_noirq()
1861 base = community->regs + community->hostown_offset; in intel_pinctrl_resume_noirq()
1862 for (gpp = 0; gpp < community->ngpps; gpp++) in intel_pinctrl_resume_noirq()