Lines Matching +full:warn +full:- +full:soc +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013, Intel Corporation
25 #include <linux/pinctrl/pinconf-generic.h>
27 #include "pinctrl-intel.h"
560 for (i = 0; i < vg->ncommunities; i++) { in byt_get_community()
561 comm = vg->communities + i; in byt_get_community()
562 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) in byt_get_community()
578 offset -= comm->pin_base; in byt_gpio_reg()
587 reg_offset = comm->pad_map[offset] * 16; in byt_gpio_reg()
591 return comm->pad_regs + reg_offset + reg; in byt_gpio_reg()
598 return vg->soc->ngroups; in byt_get_groups_count()
606 return vg->soc->groups[selector].grp.name; in byt_get_group_name()
616 *pins = vg->soc->groups[selector].grp.pins; in byt_get_group_pins()
617 *num_pins = vg->soc->groups[selector].grp.npins; in byt_get_group_pins()
632 return vg->soc->nfunctions; in byt_get_functions_count()
640 return vg->soc->functions[selector].name; in byt_get_function_name()
650 *groups = vg->soc->functions[selector].groups; in byt_get_function_groups()
651 *num_groups = vg->soc->functions[selector].ngroups; in byt_get_function_groups()
671 dev_warn(vg->dev, in byt_set_group_simple_mux()
701 dev_warn(vg->dev, in byt_set_group_mixed_mux()
720 const struct intel_function func = vg->soc->functions[func_selector]; in byt_set_mux()
721 const struct intel_pingroup group = vg->soc->groups[group_selector]; in byt_set_mux()
735 /* SCORE pin 92-93 */ in byt_get_gpio_mux()
736 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && in byt_get_gpio_mux()
740 /* SUS pin 11-21 */ in byt_get_gpio_mux()
741 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && in byt_get_gpio_mux()
757 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ in byt_gpio_clear_triggering()
794 dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset); in byt_gpio_request_enable()
799 pm_runtime_get(vg->dev); in byt_gpio_request_enable()
811 pm_runtime_put(vg->dev); in byt_gpio_disable_free()
826 dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output"); in byt_gpio_direct_irq_check()
901 return -EINVAL; in byt_set_pull_strength()
928 return -EINVAL; in byt_pin_config_get()
933 return -EINVAL; in byt_pin_config_get()
941 return -EINVAL; in byt_pin_config_get()
948 return -EINVAL; in byt_pin_config_get()
977 return -EINVAL; in byt_pin_config_get()
982 return -ENOTSUPP; in byt_pin_config_get()
1024 * chip is not in input mode, set it and warn about it. in byt_pin_config_set()
1029 dev_warn(vg->dev, in byt_pin_config_set()
1046 * chip is not in input mode, set it and warn about it. in byt_pin_config_set()
1051 dev_warn(vg->dev, in byt_pin_config_set()
1100 ret = -EINVAL; in byt_pin_config_set()
1108 ret = -ENOTSUPP; in byt_pin_config_set()
1177 return -EINVAL; in byt_gpio_get_direction()
1188 return -EINVAL; in byt_gpio_get_direction()
1246 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_dbg_show()
1256 pin = vg->soc->pins[i].number; in byt_gpio_dbg_show()
1312 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", in byt_gpio_dbg_show()
1318 comm->pad_map[i], comm->pad_map[i] * 16, in byt_gpio_dbg_show()
1322 conf0 & BYT_TRIG_LVL ? " level" : " "); in byt_gpio_dbg_show()
1325 seq_printf(s, " %-4s %-3s", pull, pull_str); in byt_gpio_dbg_show()
1330 seq_puts(s, " open-drain"); in byt_gpio_dbg_show()
1426 return -EINVAL; in byt_irq_type()
1431 WARN(value & BYT_DIRECT_IRQ_EN, in byt_irq_type()
1434 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits in byt_irq_type()
1435 * are used to indicate high and low level triggering in byt_irq_type()
1456 .name = "BYT-GPIO",
1475 for (base = 0; base < vg->chip.ngpio; base += 32) { in byt_gpio_irq_handler()
1479 dev_warn(vg->dev, in byt_gpio_irq_handler()
1489 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); in byt_gpio_irq_handler()
1491 chip->irq_eoi(data); in byt_gpio_irq_handler()
1500 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, in byt_direct_irq_sanity_check()
1504 dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin); in byt_direct_irq_sanity_check()
1508 direct_irq = match - direct_irq_mux; in byt_direct_irq_sanity_check()
1509 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ in byt_direct_irq_sanity_check()
1510 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; in byt_direct_irq_sanity_check()
1511 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, in byt_direct_irq_sanity_check()
1516 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ in byt_direct_irq_sanity_check()
1518 * 0x800, to one of the IO-APIC pins according to the mux registers. in byt_direct_irq_sanity_check()
1523 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, in byt_direct_irq_sanity_check()
1524 * selecting edge mode operation then on the first edge the IO-APIC pin goes in byt_direct_irq_sanity_check()
1525 * high, but since no write-to-clear write will be done to the IRQ status reg in byt_direct_irq_sanity_check()
1531 dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n", in byt_direct_irq_sanity_check()
1553 for (i = 0; i < vg->soc->npins; i++) { in byt_init_irq_valid_mask()
1554 unsigned int pin = vg->soc->pins[i].number; in byt_init_irq_valid_mask()
1558 dev_warn(vg->dev, in byt_init_irq_valid_mask()
1575 dev_dbg(vg->dev, "disabling GPIO %d\n", i); in byt_init_irq_valid_mask()
1587 for (base = 0; base < vg->soc->npins; base += 32) { in byt_gpio_irq_init_hw()
1591 dev_warn(vg->dev, in byt_gpio_irq_init_hw()
1602 dev_err(vg->dev, in byt_gpio_irq_init_hw()
1613 struct device *dev = vg->dev; in byt_gpio_add_pin_ranges()
1616 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); in byt_gpio_add_pin_ranges()
1625 struct platform_device *pdev = to_platform_device(vg->dev); in byt_gpio_probe()
1630 vg->chip = byt_gpio_chip; in byt_gpio_probe()
1631 gc = &vg->chip; in byt_gpio_probe()
1632 gc->label = dev_name(vg->dev); in byt_gpio_probe()
1633 gc->base = -1; in byt_gpio_probe()
1634 gc->can_sleep = false; in byt_gpio_probe()
1635 gc->add_pin_ranges = byt_gpio_add_pin_ranges; in byt_gpio_probe()
1636 gc->parent = vg->dev; in byt_gpio_probe()
1637 gc->ngpio = vg->soc->npins; in byt_gpio_probe()
1640 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), in byt_gpio_probe()
1642 if (!vg->context.pads) in byt_gpio_probe()
1643 return -ENOMEM; in byt_gpio_probe()
1651 girq = &gc->irq; in byt_gpio_probe()
1653 girq->init_hw = byt_gpio_irq_init_hw; in byt_gpio_probe()
1654 girq->init_valid_mask = byt_init_irq_valid_mask; in byt_gpio_probe()
1655 girq->parent_handler = byt_gpio_irq_handler; in byt_gpio_probe()
1656 girq->num_parents = 1; in byt_gpio_probe()
1657 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, in byt_gpio_probe()
1658 sizeof(*girq->parents), GFP_KERNEL); in byt_gpio_probe()
1659 if (!girq->parents) in byt_gpio_probe()
1660 return -ENOMEM; in byt_gpio_probe()
1661 girq->parents[0] = irq; in byt_gpio_probe()
1662 girq->default_type = IRQ_TYPE_NONE; in byt_gpio_probe()
1663 girq->handler = handle_bad_irq; in byt_gpio_probe()
1666 ret = devm_gpiochip_add_data(vg->dev, gc, vg); in byt_gpio_probe()
1668 dev_err(vg->dev, "failed adding byt-gpio chip\n"); in byt_gpio_probe()
1676 const struct intel_pinctrl_soc_data *soc) in byt_set_soc_data() argument
1678 struct platform_device *pdev = to_platform_device(vg->dev); in byt_set_soc_data()
1681 vg->soc = soc; in byt_set_soc_data()
1683 vg->ncommunities = vg->soc->ncommunities; in byt_set_soc_data()
1684 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities, in byt_set_soc_data()
1685 sizeof(*vg->communities), GFP_KERNEL); in byt_set_soc_data()
1686 if (!vg->communities) in byt_set_soc_data()
1687 return -ENOMEM; in byt_set_soc_data()
1689 for (i = 0; i < vg->soc->ncommunities; i++) { in byt_set_soc_data()
1690 struct intel_community *comm = vg->communities + i; in byt_set_soc_data()
1692 *comm = vg->soc->communities[i]; in byt_set_soc_data()
1694 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); in byt_set_soc_data()
1695 if (IS_ERR(comm->pad_regs)) in byt_set_soc_data()
1696 return PTR_ERR(comm->pad_regs); in byt_set_soc_data()
1711 struct device *dev = &pdev->dev; in byt_pinctrl_probe()
1721 return -ENOMEM; in byt_pinctrl_probe()
1723 vg->dev = dev; in byt_pinctrl_probe()
1726 dev_err(dev, "failed to set soc data\n"); in byt_pinctrl_probe()
1730 vg->pctldesc = byt_pinctrl_desc; in byt_pinctrl_probe()
1731 vg->pctldesc.name = dev_name(dev); in byt_pinctrl_probe()
1732 vg->pctldesc.pins = vg->soc->pins; in byt_pinctrl_probe()
1733 vg->pctldesc.npins = vg->soc->npins; in byt_pinctrl_probe()
1735 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); in byt_pinctrl_probe()
1736 if (IS_ERR(vg->pctldev)) { in byt_pinctrl_probe()
1738 return PTR_ERR(vg->pctldev); in byt_pinctrl_probe()
1760 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_suspend()
1763 unsigned int pin = vg->soc->pins[i].number; in byt_gpio_suspend()
1767 dev_warn(vg->dev, in byt_gpio_suspend()
1773 vg->context.pads[i].conf0 = value; in byt_gpio_suspend()
1777 vg->context.pads[i].val = value; in byt_gpio_suspend()
1792 for (i = 0; i < vg->soc->npins; i++) { in byt_gpio_resume()
1795 unsigned int pin = vg->soc->pins[i].number; in byt_gpio_resume()
1799 dev_warn(vg->dev, in byt_gpio_resume()
1806 vg->context.pads[i].conf0) { in byt_gpio_resume()
1808 value |= vg->context.pads[i].conf0; in byt_gpio_resume()
1816 vg->context.pads[i].val) { in byt_gpio_resume()
1820 v |= vg->context.pads[i].val; in byt_gpio_resume()