1 // SPDX-License-Identifier: GPL-2.0-only
7  * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
10  *				gpio_a (8 - 11)
11  *				+----------
13  *		gpio_a (8-11)	|	gpio_b (0 - 3)
14  *	------------------------+-------+----------
16  *					|	pwm (0 - 3)
17  *					+----------
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
31 #include "../pinctrl-utils.h"
33 #define NSP_MUX_BASE0	0x00
34 #define NSP_MUX_BASE1	0x01
35 #define NSP_MUX_BASE2	0x02
39  * @base: base 0 or base 1
92  * nsp IOMUX pinctrl core
144 	NSP_PIN_DESC(0, "spi_clk", 1),
162 	NSP_PIN_DESC(18, "synce", 0),
163 	NSP_PIN_DESC(19, "sata0_led", 0),
164 	NSP_PIN_DESC(20, "sata1_led", 0),
170 	NSP_PIN_DESC(26, "p5_led0", 0),
171 	NSP_PIN_DESC(27, "p5_led1", 0),
176 	NSP_PIN_DESC(32, "nand_ale", 0),
177 	NSP_PIN_DESC(33, "nand_ce0", 0),
178 	NSP_PIN_DESC(34, "nand_r/b", 0),
179 	NSP_PIN_DESC(35, "nand_dq0", 0),
180 	NSP_PIN_DESC(36, "nand_dq1", 0),
181 	NSP_PIN_DESC(37, "nand_dq2", 0),
182 	NSP_PIN_DESC(38, "nand_dq3", 0),
183 	NSP_PIN_DESC(39, "nand_dq4", 0),
184 	NSP_PIN_DESC(40, "nand_dq5", 0),
185 	NSP_PIN_DESC(41, "nand_dq6", 0),
186 	NSP_PIN_DESC(42, "nand_dq7", 0),
193 static const unsigned int spi_pins[] = {0, 1, 2, 3};
236 	NSP_PIN_GROUP(spi, NSP_MUX_BASE0, 0, 0x0f, 0x00),
237 	NSP_PIN_GROUP(i2c, NSP_MUX_BASE0, 3, 0x03, 0x00),
238 	NSP_PIN_GROUP(mdio, NSP_MUX_BASE0, 5, 0x03, 0x00),
239 	NSP_PIN_GROUP(gpio_b_0, NSP_MUX_BASE0, 7, 0x01, 0x00),
240 	NSP_PIN_GROUP(pwm0, NSP_MUX_BASE1, 0, 0x01, 0x01),
241 	NSP_PIN_GROUP(gpio_b_1, NSP_MUX_BASE0, 8, 0x01, 0x00),
242 	NSP_PIN_GROUP(pwm1, NSP_MUX_BASE1, 1, 0x01, 0x01),
243 	NSP_PIN_GROUP(gpio_b_2, NSP_MUX_BASE0, 9, 0x01, 0x00),
244 	NSP_PIN_GROUP(pwm2, NSP_MUX_BASE1, 2, 0x01, 0x01),
245 	NSP_PIN_GROUP(gpio_b_3, NSP_MUX_BASE0, 10, 0x01, 0x00),
246 	NSP_PIN_GROUP(pwm3, NSP_MUX_BASE1, 3, 0x01, 0x01),
247 	NSP_PIN_GROUP(uart1, NSP_MUX_BASE0, 11, 0x0f, 0x00),
248 	NSP_PIN_GROUP(uart2, NSP_MUX_BASE0, 15, 0x03, 0x00),
249 	NSP_PIN_GROUP(synce, NSP_MUX_BASE0, 17, 0x01, 0x01),
250 	NSP_PIN_GROUP(sata0_led, NSP_MUX_BASE0, 18, 0x01, 0x01),
251 	NSP_PIN_GROUP(sata1_led, NSP_MUX_BASE0, 19, 0x01, 0x01),
252 	NSP_PIN_GROUP(xtal_out, NSP_MUX_BASE0, 20, 0x01, 0x00),
253 	NSP_PIN_GROUP(sdio_pwr, NSP_MUX_BASE0, 21, 0x01, 0x00),
254 	NSP_PIN_GROUP(sdio_1p8v, NSP_MUX_BASE0, 22, 0x01, 0x00),
255 	NSP_PIN_GROUP(switch_p05_led0, NSP_MUX_BASE0, 26, 0x01, 0x01),
256 	NSP_PIN_GROUP(switch_p05_led1, NSP_MUX_BASE0, 27, 0x01, 0x01),
257 	NSP_PIN_GROUP(nand, NSP_MUX_BASE2, 0, 0x01, 0x00),
258 	NSP_PIN_GROUP(emmc, NSP_MUX_BASE2, 0, 0x01, 0x01)
312 	struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in nsp_get_groups_count()  local
314 	return pinctrl->num_groups;  in nsp_get_groups_count()
320 	struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in nsp_get_group_name()  local
322 	return pinctrl->groups[selector].name;  in nsp_get_group_name()
329 	struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in nsp_get_group_pins()  local
331 	*pins = pinctrl->groups[selector].pins;  in nsp_get_group_pins()
332 	*num_pins = pinctrl->groups[selector].num_pins;  in nsp_get_group_pins()
334 	return 0;  in nsp_get_group_pins()
340 	seq_printf(s, " %s", dev_name(pctrl_dev->dev));  in nsp_pin_dbg_show()
354 	struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in nsp_get_functions_count()  local
356 	return pinctrl->num_functions;  in nsp_get_functions_count()
362 	struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in nsp_get_function_name()  local
364 	return pinctrl->functions[selector].name;  in nsp_get_function_name()
372 	struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in nsp_get_function_groups()  local
374 	*groups = pinctrl->functions[selector].groups;  in nsp_get_function_groups()
375 	*num_groups = pinctrl->functions[selector].num_groups;  in nsp_get_function_groups()
377 	return 0;  in nsp_get_function_groups()
380 static int nsp_pinmux_set(struct nsp_pinctrl *pinctrl,  in nsp_pinmux_set()  argument
385 	const struct nsp_mux *mux = &grp->mux;  in nsp_pinmux_set()
391 	for (i = 0; i < pinctrl->num_groups; i++) {  in nsp_pinmux_set()
392 		if ((mux->shift != mux_log[i].mux.shift) ||  in nsp_pinmux_set()
393 			(mux->base != mux_log[i].mux.base))  in nsp_pinmux_set()
404 		if (mux_log[i].mux.alt != mux->alt) {  in nsp_pinmux_set()
405 			dev_err(pinctrl->dev,  in nsp_pinmux_set()
407 			dev_err(pinctrl->dev, "func:%s grp:%s\n",  in nsp_pinmux_set()
408 				func->name, grp->name);  in nsp_pinmux_set()
409 			return -EINVAL;  in nsp_pinmux_set()
412 		return 0;  in nsp_pinmux_set()
414 	if (i == pinctrl->num_groups)  in nsp_pinmux_set()
415 		return -EINVAL;  in nsp_pinmux_set()
417 	mask = mux->mask;  in nsp_pinmux_set()
418 	mux_log[i].mux.alt = mux->alt;  in nsp_pinmux_set()
421 	switch (mux->base) {  in nsp_pinmux_set()
423 		base_address = pinctrl->base0;  in nsp_pinmux_set()
427 		base_address = pinctrl->base1;  in nsp_pinmux_set()
431 		base_address = pinctrl->base2;  in nsp_pinmux_set()
435 		return -EINVAL;  in nsp_pinmux_set()
438 	spin_lock_irqsave(&pinctrl->lock, flags);  in nsp_pinmux_set()
440 	val &= ~(mask << grp->mux.shift);  in nsp_pinmux_set()
441 	val |= grp->mux.alt << grp->mux.shift;  in nsp_pinmux_set()
443 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in nsp_pinmux_set()
445 	return 0;  in nsp_pinmux_set()
451 	struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in nsp_pinmux_enable()  local
455 	if (grp_select >= pinctrl->num_groups ||  in nsp_pinmux_enable()
456 	    func_select >= pinctrl->num_functions)  in nsp_pinmux_enable()
457 		return -EINVAL;  in nsp_pinmux_enable()
459 	func = &pinctrl->functions[func_select];  in nsp_pinmux_enable()
460 	grp = &pinctrl->groups[grp_select];  in nsp_pinmux_enable()
462 	dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",  in nsp_pinmux_enable()
463 		func_select, func->name, grp_select, grp->name);  in nsp_pinmux_enable()
465 	dev_dbg(pctrl_dev->dev, "shift:%u alt:%u\n", grp->mux.shift,  in nsp_pinmux_enable()
466 		grp->mux.alt);  in nsp_pinmux_enable()
468 	return nsp_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);  in nsp_pinmux_enable()
476 	struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in nsp_gpio_request_enable()  local
477 	u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;  in nsp_gpio_request_enable()
481 	spin_lock_irqsave(&pinctrl->lock, flags);  in nsp_gpio_request_enable()
482 	val = readl(pinctrl->base0);  in nsp_gpio_request_enable()
486 		writel(val, pinctrl->base0);  in nsp_gpio_request_enable()
488 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in nsp_gpio_request_enable()
490 	return 0;  in nsp_gpio_request_enable()
497 	struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);  in nsp_gpio_disable_free()  local
498 	u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;  in nsp_gpio_disable_free()
502 	spin_lock_irqsave(&pinctrl->lock, flags);  in nsp_gpio_disable_free()
503 	val = readl(pinctrl->base0);  in nsp_gpio_disable_free()
508 		writel(val, pinctrl->base0);  in nsp_gpio_disable_free()
510 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in nsp_gpio_disable_free()
523 	.name = "nsp-pinmux",
528 static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl)  in nsp_mux_log_init()  argument
534 	pinctrl->mux_log = devm_kcalloc(pinctrl->dev, no_of_groups,  in nsp_mux_log_init()
537 	if (!pinctrl->mux_log)  in nsp_mux_log_init()
538 		return -ENOMEM;  in nsp_mux_log_init()
540 	for (i = 0; i < no_of_groups; i++) {  in nsp_mux_log_init()
541 		log = &pinctrl->mux_log[i];  in nsp_mux_log_init()
542 		log->mux.base = nsp_pin_groups[i].mux.base;  in nsp_mux_log_init()
543 		log->mux.shift = nsp_pin_groups[i].mux.shift;  in nsp_mux_log_init()
544 		log->mux.alt = 0;  in nsp_mux_log_init()
545 		log->is_configured = false;  in nsp_mux_log_init()
548 	return 0;  in nsp_mux_log_init()
553 	struct nsp_pinctrl *pinctrl;  in nsp_pinmux_probe()  local
559 	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);  in nsp_pinmux_probe()
560 	if (!pinctrl)  in nsp_pinmux_probe()
561 		return -ENOMEM;  in nsp_pinmux_probe()
562 	pinctrl->dev = &pdev->dev;  in nsp_pinmux_probe()
563 	platform_set_drvdata(pdev, pinctrl);  in nsp_pinmux_probe()
564 	spin_lock_init(&pinctrl->lock);  in nsp_pinmux_probe()
566 	pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);  in nsp_pinmux_probe()
567 	if (IS_ERR(pinctrl->base0))  in nsp_pinmux_probe()
568 		return PTR_ERR(pinctrl->base0);  in nsp_pinmux_probe()
572 		return -EINVAL;  in nsp_pinmux_probe()
573 	pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,  in nsp_pinmux_probe()
575 	if (!pinctrl->base1) {  in nsp_pinmux_probe()
576 		dev_err(&pdev->dev, "unable to map I/O space\n");  in nsp_pinmux_probe()
577 		return -ENOMEM;  in nsp_pinmux_probe()
580 	pinctrl->base2 = devm_platform_ioremap_resource(pdev, 2);  in nsp_pinmux_probe()
581 	if (IS_ERR(pinctrl->base2))  in nsp_pinmux_probe()
582 		return PTR_ERR(pinctrl->base2);  in nsp_pinmux_probe()
584 	ret = nsp_mux_log_init(pinctrl);  in nsp_pinmux_probe()
586 		dev_err(&pdev->dev, "unable to initialize IOMUX log\n");  in nsp_pinmux_probe()
590 	pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);  in nsp_pinmux_probe()
592 		return -ENOMEM;  in nsp_pinmux_probe()
594 	for (i = 0; i < num_pins; i++) {  in nsp_pinmux_probe()
600 	pinctrl->groups = nsp_pin_groups;  in nsp_pinmux_probe()
601 	pinctrl->num_groups = ARRAY_SIZE(nsp_pin_groups);  in nsp_pinmux_probe()
602 	pinctrl->functions = nsp_pin_functions;  in nsp_pinmux_probe()
603 	pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions);  in nsp_pinmux_probe()
607 	pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc,  in nsp_pinmux_probe()
608 					 pinctrl);  in nsp_pinmux_probe()
609 	if (IS_ERR(pinctrl->pctl)) {  in nsp_pinmux_probe()
610 		dev_err(&pdev->dev, "unable to register nsp IOMUX pinctrl\n");  in nsp_pinmux_probe()
611 		return PTR_ERR(pinctrl->pctl);  in nsp_pinmux_probe()
614 	return 0;  in nsp_pinmux_probe()
618 	{ .compatible = "brcm,nsp-pinmux" },
624 		.name = "nsp-pinmux",