Lines Matching +full:pinctrl +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pinctrl/pinconf.h>
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
20 #include "../pinctrl-utils.h"
98 * Northstar2 IOMUX pinctrl core
137 * @pull_shift: pull-up/pull-down control bit shift in the register
180 NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
181 NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
182 NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
183 NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
184 NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
185 NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
186 NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
187 NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
188 NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
189 NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
190 NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
191 NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
192 NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
193 NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
194 NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
195 NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
196 NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
197 NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
198 NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
199 NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
200 NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
201 NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
202 NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
203 NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
204 NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
205 NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
206 NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
207 NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
208 NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
209 NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
210 NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
211 NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
212 NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
213 NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
214 NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
215 NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
216 NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
217 NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
218 NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
219 NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
220 NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
221 NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
222 NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
223 NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
224 NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
225 NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
226 NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
227 NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
228 NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
229 NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
230 NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
231 NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
232 NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
233 NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
234 NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
235 NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
236 NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
237 NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
238 NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
239 NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
240 NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
241 NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
242 NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
243 NS2_PIN_DESC(63, "qspi_wp", 2, 0x0, 31, 30, 27, 24),
244 NS2_PIN_DESC(64, "qspi_hold", 2, 0x0, 23, 22, 19, 16),
245 NS2_PIN_DESC(65, "qspi_cs", 2, 0x0, 15, 14, 11, 8),
246 NS2_PIN_DESC(66, "qspi_sck", 2, 0x0, 7, 6, 3, 0),
247 NS2_PIN_DESC(67, "uart3_sin", 2, 0x04, 31, 30, 27, 24),
248 NS2_PIN_DESC(68, "uart3_sout", 2, 0x04, 23, 22, 19, 16),
249 NS2_PIN_DESC(69, "qspi_mosi", 2, 0x04, 15, 14, 11, 8),
250 NS2_PIN_DESC(70, "qspi_miso", 2, 0x04, 7, 6, 3, 0),
251 NS2_PIN_DESC(71, "spi0_fss", 2, 0x08, 31, 30, 27, 24),
252 NS2_PIN_DESC(72, "spi0_rxd", 2, 0x08, 23, 22, 19, 16),
253 NS2_PIN_DESC(73, "spi0_txd", 2, 0x08, 15, 14, 11, 8),
254 NS2_PIN_DESC(74, "spi0_sck", 2, 0x08, 7, 6, 3, 0),
255 NS2_PIN_DESC(75, "spi1_fss", 2, 0x0c, 31, 30, 27, 24),
256 NS2_PIN_DESC(76, "spi1_rxd", 2, 0x0c, 23, 22, 19, 16),
257 NS2_PIN_DESC(77, "spi1_txd", 2, 0x0c, 15, 14, 11, 8),
258 NS2_PIN_DESC(78, "spi1_sck", 2, 0x0c, 7, 6, 3, 0),
259 NS2_PIN_DESC(79, "sdio0_data7", 2, 0x10, 31, 30, 27, 24),
260 NS2_PIN_DESC(80, "sdio0_emmc_rst", 2, 0x10, 23, 22, 19, 16),
261 NS2_PIN_DESC(81, "sdio0_led_on", 2, 0x10, 15, 14, 11, 8),
262 NS2_PIN_DESC(82, "sdio0_wp", 2, 0x10, 7, 6, 3, 0),
263 NS2_PIN_DESC(83, "sdio0_data3", 2, 0x14, 31, 30, 27, 24),
264 NS2_PIN_DESC(84, "sdio0_data4", 2, 0x14, 23, 22, 19, 16),
265 NS2_PIN_DESC(85, "sdio0_data5", 2, 0x14, 15, 14, 11, 8),
266 NS2_PIN_DESC(86, "sdio0_data6", 2, 0x14, 7, 6, 3, 0),
267 NS2_PIN_DESC(87, "sdio0_cmd", 2, 0x18, 31, 30, 27, 24),
268 NS2_PIN_DESC(88, "sdio0_data0", 2, 0x18, 23, 22, 19, 16),
269 NS2_PIN_DESC(89, "sdio0_data1", 2, 0x18, 15, 14, 11, 8),
270 NS2_PIN_DESC(90, "sdio0_data2", 2, 0x18, 7, 6, 3, 0),
271 NS2_PIN_DESC(91, "sdio1_led_on", 2, 0x1c, 31, 30, 27, 24),
272 NS2_PIN_DESC(92, "sdio1_wp", 2, 0x1c, 23, 22, 19, 16),
273 NS2_PIN_DESC(93, "sdio0_cd_l", 2, 0x1c, 15, 14, 11, 8),
274 NS2_PIN_DESC(94, "sdio0_clk", 2, 0x1c, 7, 6, 3, 0),
275 NS2_PIN_DESC(95, "sdio1_data5", 2, 0x20, 31, 30, 27, 24),
276 NS2_PIN_DESC(96, "sdio1_data6", 2, 0x20, 23, 22, 19, 16),
277 NS2_PIN_DESC(97, "sdio1_data7", 2, 0x20, 15, 14, 11, 8),
278 NS2_PIN_DESC(98, "sdio1_emmc_rst", 2, 0x20, 7, 6, 3, 0),
279 NS2_PIN_DESC(99, "sdio1_data1", 2, 0x24, 31, 30, 27, 24),
280 NS2_PIN_DESC(100, "sdio1_data2", 2, 0x24, 23, 22, 19, 16),
281 NS2_PIN_DESC(101, "sdio1_data3", 2, 0x24, 15, 14, 11, 8),
282 NS2_PIN_DESC(102, "sdio1_data4", 2, 0x24, 7, 6, 3, 0),
283 NS2_PIN_DESC(103, "sdio1_cd_l", 2, 0x28, 31, 30, 27, 24),
284 NS2_PIN_DESC(104, "sdio1_clk", 2, 0x28, 23, 22, 19, 16),
285 NS2_PIN_DESC(105, "sdio1_cmd", 2, 0x28, 15, 14, 11, 8),
286 NS2_PIN_DESC(106, "sdio1_data0", 2, 0x28, 7, 6, 3, 0),
287 NS2_PIN_DESC(107, "ext_mdio_0", 2, 0x2c, 15, 14, 11, 8),
288 NS2_PIN_DESC(108, "ext_mdc_0", 2, 0x2c, 7, 6, 3, 0),
289 NS2_PIN_DESC(109, "usb3_p1_vbus_ppc", 2, 0x34, 31, 30, 27, 24),
290 NS2_PIN_DESC(110, "usb3_p1_overcurrent", 2, 0x34, 23, 22, 19, 16),
291 NS2_PIN_DESC(111, "usb3_p0_vbus_ppc", 2, 0x34, 15, 14, 11, 8),
292 NS2_PIN_DESC(112, "usb3_p0_overcurrent", 2, 0x34, 7, 6, 3, 0),
293 NS2_PIN_DESC(113, "usb2_presence_indication", 2, 0x38, 31, 30, 27, 24),
294 NS2_PIN_DESC(114, "usb2_vbus_present", 2, 0x38, 23, 22, 19, 16),
295 NS2_PIN_DESC(115, "usb2_vbus_ppc", 2, 0x38, 15, 14, 11, 8),
296 NS2_PIN_DESC(116, "usb2_overcurrent", 2, 0x38, 7, 6, 3, 0),
297 NS2_PIN_DESC(117, "sata_led1", 2, 0x3c, 15, 14, 11, 8),
298 NS2_PIN_DESC(118, "sata_led0", 2, 0x3c, 7, 6, 3, 0),
305 static const unsigned int nand_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
307 static const unsigned int nor_data_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
387 NS2_PIN_GROUP(nor_adv, 0, 4, 30, 3, 2),
391 NS2_PIN_GROUP(nor_addr_0_3, 0, 4, 28, 3, 2),
395 NS2_PIN_GROUP(nor_addr_4_5, 0, 4, 26, 3, 2),
399 NS2_PIN_GROUP(nor_addr_6_7, 0, 4, 24, 3, 2),
403 NS2_PIN_GROUP(nor_addr_8_9, 0, 4, 22, 3, 2),
407 NS2_PIN_GROUP(nor_addr_10_11, 0, 4, 20, 3, 2),
411 NS2_PIN_GROUP(nor_addr_12_15, 0, 4, 18, 3, 2),
436 NS2_PIN_GROUP(pwm_2, 1, 0, 2, 1, 1),
495 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_groups_count() local
497 return pinctrl->num_groups; in ns2_get_groups_count()
503 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_group_name() local
505 return pinctrl->groups[selector].name; in ns2_get_group_name()
512 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_group_pins() local
514 *pins = pinctrl->groups[selector].pins; in ns2_get_group_pins()
515 *num_pins = pinctrl->groups[selector].num_pins; in ns2_get_group_pins()
523 seq_printf(s, " %s", dev_name(pctrl_dev->dev)); in ns2_pin_dbg_show()
537 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_functions_count() local
539 return pinctrl->num_functions; in ns2_get_functions_count()
545 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_function_name() local
547 return pinctrl->functions[selector].name; in ns2_get_function_name()
555 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_function_groups() local
557 *groups = pinctrl->functions[selector].groups; in ns2_get_function_groups()
558 *num_groups = pinctrl->functions[selector].num_groups; in ns2_get_function_groups()
563 static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl, in ns2_pinmux_set() argument
568 const struct ns2_mux *mux = &grp->mux; in ns2_pinmux_set()
575 if ((mux->shift != mux_log[i].mux.shift) || in ns2_pinmux_set()
576 (mux->base != mux_log[i].mux.base) || in ns2_pinmux_set()
577 (mux->offset != mux_log[i].mux.offset)) in ns2_pinmux_set()
588 if (mux_log[i].mux.alt != mux->alt) { in ns2_pinmux_set()
589 dev_err(pinctrl->dev, in ns2_pinmux_set()
591 dev_err(pinctrl->dev, "func:%s grp:%s\n", in ns2_pinmux_set()
592 func->name, grp->name); in ns2_pinmux_set()
593 return -EINVAL; in ns2_pinmux_set()
599 return -EINVAL; in ns2_pinmux_set()
601 mask = mux->mask; in ns2_pinmux_set()
602 mux_log[i].mux.alt = mux->alt; in ns2_pinmux_set()
605 switch (mux->base) { in ns2_pinmux_set()
607 base_address = pinctrl->base0; in ns2_pinmux_set()
611 base_address = pinctrl->base1; in ns2_pinmux_set()
615 return -EINVAL; in ns2_pinmux_set()
618 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pinmux_set()
619 val = readl(base_address + grp->mux.offset); in ns2_pinmux_set()
620 val &= ~(mask << grp->mux.shift); in ns2_pinmux_set()
621 val |= grp->mux.alt << grp->mux.shift; in ns2_pinmux_set()
622 writel(val, (base_address + grp->mux.offset)); in ns2_pinmux_set()
623 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pinmux_set()
631 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_pinmux_enable() local
635 if (grp_select >= pinctrl->num_groups || in ns2_pinmux_enable()
636 func_select >= pinctrl->num_functions) in ns2_pinmux_enable()
637 return -EINVAL; in ns2_pinmux_enable()
639 func = &pinctrl->functions[func_select]; in ns2_pinmux_enable()
640 grp = &pinctrl->groups[grp_select]; in ns2_pinmux_enable()
642 dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n", in ns2_pinmux_enable()
643 func_select, func->name, grp_select, grp->name); in ns2_pinmux_enable()
645 dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n", in ns2_pinmux_enable()
646 grp->mux.offset, grp->mux.shift, grp->mux.alt); in ns2_pinmux_enable()
648 return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log); in ns2_pinmux_enable()
654 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_set_enable() local
655 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_set_enable()
660 base_address = pinctrl->pinconf_base; in ns2_pin_set_enable()
661 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_set_enable()
662 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_enable()
663 val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en); in ns2_pin_set_enable()
666 val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en; in ns2_pin_set_enable()
668 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_enable()
669 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_set_enable()
671 dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable); in ns2_pin_set_enable()
677 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_get_enable() local
678 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_get_enable()
682 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_get_enable()
683 enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); in ns2_pin_get_enable()
684 enable = (enable >> pin_data->pin_conf.input_en) & in ns2_pin_get_enable()
686 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_get_enable()
693 dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable); in ns2_pin_get_enable()
700 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_set_slew() local
701 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_set_slew()
706 base_address = pinctrl->pinconf_base; in ns2_pin_set_slew()
707 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_set_slew()
708 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_slew()
709 val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift); in ns2_pin_set_slew()
712 val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift; in ns2_pin_set_slew()
714 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_slew()
715 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_set_slew()
717 dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew); in ns2_pin_set_slew()
724 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_get_slew() local
725 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_get_slew()
729 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_get_slew()
730 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); in ns2_pin_get_slew()
731 *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK; in ns2_pin_get_slew()
732 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_get_slew()
734 dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew); in ns2_pin_get_slew()
741 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_set_pull() local
742 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_set_pull()
747 base_address = pinctrl->pinconf_base; in ns2_pin_set_pull()
748 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_set_pull()
749 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_pull()
750 val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift); in ns2_pin_set_pull()
753 val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift; in ns2_pin_set_pull()
755 val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift; in ns2_pin_set_pull()
756 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_pull()
757 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_set_pull()
759 dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n", in ns2_pin_set_pull()
768 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_get_pull() local
769 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_get_pull()
773 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_get_pull()
774 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); in ns2_pin_get_pull()
775 val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK; in ns2_pin_get_pull()
784 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_get_pull()
790 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_set_strength() local
791 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_set_strength()
797 if (strength < 2 || strength > 16 || (strength % 2)) in ns2_pin_set_strength()
798 return -ENOTSUPP; in ns2_pin_set_strength()
800 base_address = pinctrl->pinconf_base; in ns2_pin_set_strength()
801 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_set_strength()
802 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_strength()
803 val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift); in ns2_pin_set_strength()
804 val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift; in ns2_pin_set_strength()
805 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_strength()
806 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_set_strength()
808 dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n", in ns2_pin_set_strength()
816 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_get_strength() local
817 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_get_strength()
821 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_get_strength()
822 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); in ns2_pin_get_strength()
823 *strength = (val >> pin_data->pin_conf.drive_shift) & in ns2_pin_get_strength()
825 *strength = (*strength + 1) * 2; in ns2_pin_get_strength()
826 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_get_strength()
828 dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n", in ns2_pin_get_strength()
836 struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data; in ns2_pin_config_get()
842 if (pin_data->pin_conf.base == -1) in ns2_pin_config_get()
843 return -ENOTSUPP; in ns2_pin_config_get()
851 return -EINVAL; in ns2_pin_config_get()
858 return -EINVAL; in ns2_pin_config_get()
865 return -EINVAL; in ns2_pin_config_get()
886 return -EINVAL; in ns2_pin_config_get()
889 return -ENOTSUPP; in ns2_pin_config_get()
896 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_config_set()
900 int ret = -ENOTSUPP; in ns2_pin_config_set()
902 if (pin_data->pin_conf.base == -1) in ns2_pin_config_set()
903 return -ENOTSUPP; in ns2_pin_config_set()
947 dev_err(pctrldev->dev, "invalid configuration\n"); in ns2_pin_config_set()
948 return -ENOTSUPP; in ns2_pin_config_set()
968 .name = "ns2-pinmux",
974 static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl) in ns2_mux_log_init() argument
979 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX, in ns2_mux_log_init()
982 if (!pinctrl->mux_log) in ns2_mux_log_init()
983 return -ENOMEM; in ns2_mux_log_init()
986 pinctrl->mux_log[i].is_configured = false; in ns2_mux_log_init()
988 log = &pinctrl->mux_log[0]; in ns2_mux_log_init()
989 log->mux.base = NS2_PIN_MUX_BASE0; in ns2_mux_log_init()
990 log->mux.offset = 0; in ns2_mux_log_init()
991 log->mux.shift = 31; in ns2_mux_log_init()
992 log->mux.alt = 0; in ns2_mux_log_init()
999 for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) { in ns2_mux_log_init()
1000 log = &pinctrl->mux_log[i]; in ns2_mux_log_init()
1001 log->mux.base = NS2_PIN_MUX_BASE0; in ns2_mux_log_init()
1002 log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET; in ns2_mux_log_init()
1003 log->mux.shift = 32 - (i * 2); in ns2_mux_log_init()
1004 log->mux.alt = 0; in ns2_mux_log_init()
1012 log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i]; in ns2_mux_log_init()
1013 log->mux.base = NS2_PIN_MUX_BASE1; in ns2_mux_log_init()
1014 log->mux.offset = 0; in ns2_mux_log_init()
1015 log->mux.shift = i; in ns2_mux_log_init()
1016 log->mux.alt = 0; in ns2_mux_log_init()
1023 struct ns2_pinctrl *pinctrl; in ns2_pinmux_probe() local
1029 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); in ns2_pinmux_probe()
1030 if (!pinctrl) in ns2_pinmux_probe()
1031 return -ENOMEM; in ns2_pinmux_probe()
1033 pinctrl->dev = &pdev->dev; in ns2_pinmux_probe()
1034 platform_set_drvdata(pdev, pinctrl); in ns2_pinmux_probe()
1035 spin_lock_init(&pinctrl->lock); in ns2_pinmux_probe()
1037 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0); in ns2_pinmux_probe()
1038 if (IS_ERR(pinctrl->base0)) in ns2_pinmux_probe()
1039 return PTR_ERR(pinctrl->base0); in ns2_pinmux_probe()
1043 return -EINVAL; in ns2_pinmux_probe()
1044 pinctrl->base1 = devm_ioremap(&pdev->dev, res->start, in ns2_pinmux_probe()
1046 if (!pinctrl->base1) { in ns2_pinmux_probe()
1047 dev_err(&pdev->dev, "unable to map I/O space\n"); in ns2_pinmux_probe()
1048 return -ENOMEM; in ns2_pinmux_probe()
1051 pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2); in ns2_pinmux_probe()
1052 if (IS_ERR(pinctrl->pinconf_base)) in ns2_pinmux_probe()
1053 return PTR_ERR(pinctrl->pinconf_base); in ns2_pinmux_probe()
1055 ret = ns2_mux_log_init(pinctrl); in ns2_pinmux_probe()
1057 dev_err(&pdev->dev, "unable to initialize IOMUX log\n"); in ns2_pinmux_probe()
1061 pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL); in ns2_pinmux_probe()
1063 return -ENOMEM; in ns2_pinmux_probe()
1071 pinctrl->groups = ns2_pin_groups; in ns2_pinmux_probe()
1072 pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups); in ns2_pinmux_probe()
1073 pinctrl->functions = ns2_pin_functions; in ns2_pinmux_probe()
1074 pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions); in ns2_pinmux_probe()
1078 pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev, in ns2_pinmux_probe()
1079 pinctrl); in ns2_pinmux_probe()
1080 if (IS_ERR(pinctrl->pctl)) { in ns2_pinmux_probe()
1081 dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n"); in ns2_pinmux_probe()
1082 return PTR_ERR(pinctrl->pctl); in ns2_pinmux_probe()
1089 {.compatible = "brcm,ns2-pinmux"},
1095 .name = "ns2-pinmux",