1 // SPDX-License-Identifier: GPL-2.0-only
6  * corresponding mfio pin group is selected as gpio.
13 #include <linux/pinctrl/pinconf-generic.h>
20 #include "../pinctrl-utils.h"
85  * Northstar2 mux function and supported pin groups
131  * Pin configuration info
137  * @pull_shift: pull-up/pull-down control bit shift in the register
150  * Description of a pin in Northstar2
152  * @pin: pin number
153  * @name: pin name
154  * @pin_conf: pin configuration structure
157 	unsigned int pin;  member
164 	.pin = p,				\
180 	NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
181 	NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
182 	NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
183 	NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
184 	NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
185 	NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
186 	NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
187 	NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
188 	NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
189 	NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
190 	NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
191 	NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
192 	NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
193 	NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
194 	NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
195 	NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
196 	NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
197 	NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
198 	NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
199 	NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
200 	NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
201 	NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
202 	NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
203 	NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
204 	NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
205 	NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
206 	NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
207 	NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
208 	NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
209 	NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
210 	NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
211 	NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
212 	NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
213 	NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
214 	NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
215 	NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
216 	NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
217 	NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
218 	NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
219 	NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
220 	NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
221 	NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
222 	NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
223 	NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
224 	NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
225 	NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
226 	NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
227 	NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
228 	NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
229 	NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
230 	NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
231 	NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
232 	NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
233 	NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
234 	NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
235 	NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
236 	NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
237 	NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
238 	NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
239 	NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
240 	NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
241 	NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
242 	NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
379  * List of Northstar2 pin groups
497 	return pinctrl->num_groups;  in ns2_get_groups_count()
505 	return pinctrl->groups[selector].name;  in ns2_get_group_name()
514 	*pins = pinctrl->groups[selector].pins;  in ns2_get_group_pins()
515 	*num_pins = pinctrl->groups[selector].num_pins;  in ns2_get_group_pins()
523 	seq_printf(s, " %s", dev_name(pctrl_dev->dev));  in ns2_pin_dbg_show()
539 	return pinctrl->num_functions;  in ns2_get_functions_count()
547 	return pinctrl->functions[selector].name;  in ns2_get_function_name()
557 	*groups = pinctrl->functions[selector].groups;  in ns2_get_function_groups()
558 	*num_groups = pinctrl->functions[selector].num_groups;  in ns2_get_function_groups()
568 	const struct ns2_mux *mux = &grp->mux;  in ns2_pinmux_set()
570 	u32 val, mask;  in ns2_pinmux_set()  local
575 		if ((mux->shift != mux_log[i].mux.shift) ||  in ns2_pinmux_set()
576 			(mux->base != mux_log[i].mux.base) ||  in ns2_pinmux_set()
577 			(mux->offset != mux_log[i].mux.offset))  in ns2_pinmux_set()
588 		if (mux_log[i].mux.alt != mux->alt) {  in ns2_pinmux_set()
589 			dev_err(pinctrl->dev,  in ns2_pinmux_set()
591 			dev_err(pinctrl->dev, "func:%s grp:%s\n",  in ns2_pinmux_set()
592 				func->name, grp->name);  in ns2_pinmux_set()
593 			return -EINVAL;  in ns2_pinmux_set()
599 		return -EINVAL;  in ns2_pinmux_set()
601 	mask = mux->mask;  in ns2_pinmux_set()
602 	mux_log[i].mux.alt = mux->alt;  in ns2_pinmux_set()
605 	switch (mux->base) {  in ns2_pinmux_set()
607 		base_address = pinctrl->base0;  in ns2_pinmux_set()
611 		base_address = pinctrl->base1;  in ns2_pinmux_set()
615 		return -EINVAL;  in ns2_pinmux_set()
618 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pinmux_set()
619 	val = readl(base_address + grp->mux.offset);  in ns2_pinmux_set()
620 	val &= ~(mask << grp->mux.shift);  in ns2_pinmux_set()
621 	val |= grp->mux.alt << grp->mux.shift;  in ns2_pinmux_set()
622 	writel(val, (base_address + grp->mux.offset));  in ns2_pinmux_set()
623 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pinmux_set()
635 	if (grp_select >= pinctrl->num_groups ||  in ns2_pinmux_enable()
636 		func_select >= pinctrl->num_functions)  in ns2_pinmux_enable()
637 		return -EINVAL;  in ns2_pinmux_enable()
639 	func = &pinctrl->functions[func_select];  in ns2_pinmux_enable()
640 	grp = &pinctrl->groups[grp_select];  in ns2_pinmux_enable()
642 	dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",  in ns2_pinmux_enable()
643 		func_select, func->name, grp_select, grp->name);  in ns2_pinmux_enable()
645 	dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",  in ns2_pinmux_enable()
646 		grp->mux.offset, grp->mux.shift, grp->mux.alt);  in ns2_pinmux_enable()
648 	return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);  in ns2_pinmux_enable()
651 static int ns2_pin_set_enable(struct pinctrl_dev *pctrldev, unsigned int pin,  in ns2_pin_set_enable()  argument
655 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_set_enable()
657 	u32 val;  in ns2_pin_set_enable()  local
660 	base_address = pinctrl->pinconf_base;  in ns2_pin_set_enable()
661 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_set_enable()
662 	val = readl(base_address + pin_data->pin_conf.offset);  in ns2_pin_set_enable()
663 	val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en);  in ns2_pin_set_enable()
666 		val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en;  in ns2_pin_set_enable()
668 	writel(val, (base_address + pin_data->pin_conf.offset));  in ns2_pin_set_enable()
669 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_set_enable()
671 	dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable);  in ns2_pin_set_enable()
675 static int ns2_pin_get_enable(struct pinctrl_dev *pctrldev, unsigned int pin)  in ns2_pin_get_enable()  argument
678 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_get_enable()
682 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_get_enable()
683 	enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);  in ns2_pin_get_enable()
684 	enable = (enable >> pin_data->pin_conf.input_en) &  in ns2_pin_get_enable()
686 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_get_enable()
693 	dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable);  in ns2_pin_get_enable()
697 static int ns2_pin_set_slew(struct pinctrl_dev *pctrldev, unsigned int pin,  in ns2_pin_set_slew()  argument
701 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_set_slew()
703 	u32 val;  in ns2_pin_set_slew()  local
706 	base_address = pinctrl->pinconf_base;  in ns2_pin_set_slew()
707 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_set_slew()
708 	val = readl(base_address + pin_data->pin_conf.offset);  in ns2_pin_set_slew()
709 	val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift);  in ns2_pin_set_slew()
712 		val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift;  in ns2_pin_set_slew()
714 	writel(val, (base_address + pin_data->pin_conf.offset));  in ns2_pin_set_slew()
715 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_set_slew()
717 	dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew);  in ns2_pin_set_slew()
721 static int ns2_pin_get_slew(struct pinctrl_dev *pctrldev, unsigned int pin,  in ns2_pin_get_slew()  argument
725 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_get_slew()
727 	u32 val;  in ns2_pin_get_slew()  local
729 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_get_slew()
730 	val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);  in ns2_pin_get_slew()
731 	*slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK;  in ns2_pin_get_slew()
732 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_get_slew()
734 	dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew);  in ns2_pin_get_slew()
738 static int ns2_pin_set_pull(struct pinctrl_dev *pctrldev, unsigned int pin,  in ns2_pin_set_pull()  argument
742 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_set_pull()
744 	u32 val;  in ns2_pin_set_pull()  local
747 	base_address = pinctrl->pinconf_base;  in ns2_pin_set_pull()
748 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_set_pull()
749 	val = readl(base_address + pin_data->pin_conf.offset);  in ns2_pin_set_pull()
750 	val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift);  in ns2_pin_set_pull()
753 		val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift;  in ns2_pin_set_pull()
755 		val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift;  in ns2_pin_set_pull()
756 	writel(val, (base_address + pin_data->pin_conf.offset));  in ns2_pin_set_pull()
757 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_set_pull()
759 	dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n",  in ns2_pin_set_pull()
760 		pin, pull_up, pull_down);  in ns2_pin_set_pull()
765 			     unsigned int pin, bool *pull_up,  in ns2_pin_get_pull()  argument
769 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_get_pull()
771 	u32 val;  in ns2_pin_get_pull()  local
773 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_get_pull()
774 	val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);  in ns2_pin_get_pull()
775 	val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK;  in ns2_pin_get_pull()
779 	if (val == NS2_PIN_PULL_UP)  in ns2_pin_get_pull()
782 	if (val == NS2_PIN_PULL_DOWN)  in ns2_pin_get_pull()
784 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_get_pull()
787 static int ns2_pin_set_strength(struct pinctrl_dev *pctrldev, unsigned int pin,  in ns2_pin_set_strength()  argument
791 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_set_strength()
792 	u32 val;  in ns2_pin_set_strength()  local
798 		return -ENOTSUPP;  in ns2_pin_set_strength()
800 	base_address = pinctrl->pinconf_base;  in ns2_pin_set_strength()
801 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_set_strength()
802 	val = readl(base_address + pin_data->pin_conf.offset);  in ns2_pin_set_strength()
803 	val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift);  in ns2_pin_set_strength()
804 	val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift;  in ns2_pin_set_strength()
805 	writel(val, (base_address + pin_data->pin_conf.offset));  in ns2_pin_set_strength()
806 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_set_strength()
808 	dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n",  in ns2_pin_set_strength()
809 		pin, strength);  in ns2_pin_set_strength()
813 static int ns2_pin_get_strength(struct pinctrl_dev *pctrldev, unsigned int pin,  in ns2_pin_get_strength()  argument
817 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_get_strength()
818 	u32 val;  in ns2_pin_get_strength()  local
821 	spin_lock_irqsave(&pinctrl->lock, flags);  in ns2_pin_get_strength()
822 	val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);  in ns2_pin_get_strength()
823 	*strength = (val >> pin_data->pin_conf.drive_shift) &  in ns2_pin_get_strength()
826 	spin_unlock_irqrestore(&pinctrl->lock, flags);  in ns2_pin_get_strength()
828 	dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n",  in ns2_pin_get_strength()
829 		pin, *strength);  in ns2_pin_get_strength()
833 static int ns2_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,  in ns2_pin_config_get()  argument
836 	struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data;  in ns2_pin_config_get()
842 	if (pin_data->pin_conf.base == -1)  in ns2_pin_config_get()
843 		return -ENOTSUPP;  in ns2_pin_config_get()
847 		ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);  in ns2_pin_config_get()
851 			return -EINVAL;  in ns2_pin_config_get()
854 		ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);  in ns2_pin_config_get()
858 			return -EINVAL;  in ns2_pin_config_get()
861 		ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);  in ns2_pin_config_get()
865 			return -EINVAL;  in ns2_pin_config_get()
868 		ret = ns2_pin_get_strength(pctldev, pin, &arg);  in ns2_pin_config_get()
875 		ret = ns2_pin_get_slew(pctldev, pin, &arg);  in ns2_pin_config_get()
882 		ret = ns2_pin_get_enable(pctldev, pin);  in ns2_pin_config_get()
886 			return -EINVAL;  in ns2_pin_config_get()
889 		return -ENOTSUPP;  in ns2_pin_config_get()
893 static int ns2_pin_config_set(struct pinctrl_dev *pctrldev, unsigned int pin,  in ns2_pin_config_set()  argument
896 	struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;  in ns2_pin_config_set()
900 	int ret = -ENOTSUPP;  in ns2_pin_config_set()
902 	if (pin_data->pin_conf.base == -1)  in ns2_pin_config_set()
903 		return -ENOTSUPP;  in ns2_pin_config_set()
911 			ret = ns2_pin_set_pull(pctrldev, pin, false, false);  in ns2_pin_config_set()
917 			ret = ns2_pin_set_pull(pctrldev, pin, true, false);  in ns2_pin_config_set()
923 			ret = ns2_pin_set_pull(pctrldev, pin, false, true);  in ns2_pin_config_set()
929 			ret = ns2_pin_set_strength(pctrldev, pin, arg);  in ns2_pin_config_set()
935 			ret = ns2_pin_set_slew(pctrldev, pin, arg);  in ns2_pin_config_set()
941 			ret = ns2_pin_set_enable(pctrldev, pin, arg);  in ns2_pin_config_set()
947 			dev_err(pctrldev->dev, "invalid configuration\n");  in ns2_pin_config_set()
948 			return -ENOTSUPP;  in ns2_pin_config_set()
968 	.name = "ns2-pinmux",
979 	pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,  in ns2_mux_log_init()
982 	if (!pinctrl->mux_log)  in ns2_mux_log_init()
983 		return -ENOMEM;  in ns2_mux_log_init()
986 		pinctrl->mux_log[i].is_configured = false;  in ns2_mux_log_init()
988 	log = &pinctrl->mux_log[0];  in ns2_mux_log_init()
989 	log->mux.base = NS2_PIN_MUX_BASE0;  in ns2_mux_log_init()
990 	log->mux.offset = 0;  in ns2_mux_log_init()
991 	log->mux.shift = 31;  in ns2_mux_log_init()
992 	log->mux.alt = 0;  in ns2_mux_log_init()
999 	for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) {  in ns2_mux_log_init()
1000 		log = &pinctrl->mux_log[i];  in ns2_mux_log_init()
1001 		log->mux.base = NS2_PIN_MUX_BASE0;  in ns2_mux_log_init()
1002 		log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET;  in ns2_mux_log_init()
1003 		log->mux.shift = 32 - (i * 2);  in ns2_mux_log_init()
1004 		log->mux.alt = 0;  in ns2_mux_log_init()
1012 		log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];  in ns2_mux_log_init()
1013 		log->mux.base = NS2_PIN_MUX_BASE1;  in ns2_mux_log_init()
1014 		log->mux.offset = 0;  in ns2_mux_log_init()
1015 		log->mux.shift = i;  in ns2_mux_log_init()
1016 		log->mux.alt =  0;  in ns2_mux_log_init()
1029 	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);  in ns2_pinmux_probe()
1031 		return -ENOMEM;  in ns2_pinmux_probe()
1033 	pinctrl->dev = &pdev->dev;  in ns2_pinmux_probe()
1035 	spin_lock_init(&pinctrl->lock);  in ns2_pinmux_probe()
1037 	pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);  in ns2_pinmux_probe()
1038 	if (IS_ERR(pinctrl->base0))  in ns2_pinmux_probe()
1039 		return PTR_ERR(pinctrl->base0);  in ns2_pinmux_probe()
1043 		return -EINVAL;  in ns2_pinmux_probe()
1044 	pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,  in ns2_pinmux_probe()
1046 	if (!pinctrl->base1) {  in ns2_pinmux_probe()
1047 		dev_err(&pdev->dev, "unable to map I/O space\n");  in ns2_pinmux_probe()
1048 		return -ENOMEM;  in ns2_pinmux_probe()
1051 	pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);  in ns2_pinmux_probe()
1052 	if (IS_ERR(pinctrl->pinconf_base))  in ns2_pinmux_probe()
1053 		return PTR_ERR(pinctrl->pinconf_base);  in ns2_pinmux_probe()
1057 		dev_err(&pdev->dev, "unable to initialize IOMUX log\n");  in ns2_pinmux_probe()
1061 	pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);  in ns2_pinmux_probe()
1063 		return -ENOMEM;  in ns2_pinmux_probe()
1066 		pins[i].number = ns2_pins[i].pin;  in ns2_pinmux_probe()
1071 	pinctrl->groups = ns2_pin_groups;  in ns2_pinmux_probe()
1072 	pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);  in ns2_pinmux_probe()
1073 	pinctrl->functions = ns2_pin_functions;  in ns2_pinmux_probe()
1074 	pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);  in ns2_pinmux_probe()
1078 	pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,  in ns2_pinmux_probe()
1080 	if (IS_ERR(pinctrl->pctl)) {  in ns2_pinmux_probe()
1081 		dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");  in ns2_pinmux_probe()
1082 		return PTR_ERR(pinctrl->pctl);  in ns2_pinmux_probe()
1089 	{.compatible = "brcm,ns2-pinmux"},
1095 		.name = "ns2-pinmux",