29  * Lane Registers
152 #define XPSGTR_TYPE_SATA_0		2  /* SATA controller lane 0 */
153 #define XPSGTR_TYPE_SATA_1		3  /* SATA controller lane 1 */
154 #define XPSGTR_TYPE_PCIE_0		4  /* PCIe controller lane 0 */
155 #define XPSGTR_TYPE_PCIE_1		5  /* PCIe controller lane 1 */
156 #define XPSGTR_TYPE_PCIE_2		6  /* PCIe controller lane 2 */
157 #define XPSGTR_TYPE_PCIE_3		7  /* PCIe controller lane 3 */
158 #define XPSGTR_TYPE_DP_0		8  /* Display Port controller lane 0 */
159 #define XPSGTR_TYPE_DP_1		9  /* Display Port controller lane 1 */
171  * struct xpsgtr_ssc - structure to hold SSC settings for a lane
185  * struct xpsgtr_phy - representation of a lane
187  * @type: controller which uses this lane
188  * @lane: lane number
189  * @protocol: protocol in which the lane operates
197 	u8 lane;  member
278 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;  in xpsgtr_read_phy()
287 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;  in xpsgtr_write_phy()
296 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;  in xpsgtr_clr_set_phy()
333 			"lane %u (type %u, protocol %u): PLL lock timeout\n",  in xpsgtr_wait_pll_lock()
334 			gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);  in xpsgtr_wait_pll_lock()
348 	xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),  in xpsgtr_configure_pll()
351 	/* Enable lane clock sharing, if required */  in xpsgtr_configure_pll()
352 	if (gtr_phy->refclk != gtr_phy->lane) {  in xpsgtr_configure_pll()
354 		xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),  in xpsgtr_configure_pll()
388 /* Configure the lane protocol. */
394 	switch (gtr_phy->lane) {  in xpsgtr_lane_set_protocol()
410 		/* We already checked 0 <= lane <= 3 */  in xpsgtr_lane_set_protocol()
442 	writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);  in xpsgtr_phy_init_sata()
449 	u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);  in xpsgtr_phy_init_sgmii()
450 	u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);  in xpsgtr_phy_init_sgmii()
491 	 * shutdown during suspend or when gt lane is changed from current one)  in xpsgtr_phy_init_required()
521 	 * we need to configure any lane ICM_CFG to valid protocol. This  in xpsgtr_phy_tx_term_fix()
591 	 * Configure the PLL, the lane protocol, and perform protocol-specific  in xpsgtr_phy_init()
636 	 * lane 0 last.  in xpsgtr_phy_power_on()
669 /* Set the lane type and protocol based on the PHY type and instance number. */
780 	 * Get the PHY parameters from the OF arguments and derive the lane  in xpsgtr_xlate()
785 		dev_err(dev, "Invalid lane number %u\n", phy_lane);  in xpsgtr_xlate()
809 	 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type  in xpsgtr_xlate()
810 	 * is allowed to operate on the lane.  in xpsgtr_xlate()
988 		gtr_phy->lane = port;  in xpsgtr_probe()