381 	ret = regmap_field_write(wiz->por_en, 0x1);  in wiz_reset()
387 	ret = regmap_field_write(wiz->por_en, 0x0);  in wiz_reset()
404 			ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);  in wiz_p_mac_div_sel()
408 			ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);  in wiz_p_mac_div_sel()
433 			ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);  in wiz_mode_select()
434 			ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);  in wiz_mode_select()
435 			ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);  in wiz_mode_select()
439 		ret = regmap_field_write(wiz->p_standard_mode[i], mode);  in wiz_mode_select()
454 		ret = regmap_field_write(wiz->p_align[i], enable);  in wiz_init_raw_interface()
458 		ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);  in wiz_init_raw_interface()
684 	regmap_field_write(phy_en_refclk, 1);  in wiz_phy_en_refclk_enable()
694 	regmap_field_write(phy_en_refclk, 0);  in wiz_phy_en_refclk_disable()
773 	return regmap_field_write(field, val);  in wiz_clk_mux_set_parent()
928 	return regmap_field_write(field, val);  in wiz_clk_div_set_rate()
1070 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);  in wiz_clock_init()
1072 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);  in wiz_clock_init()
1079 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);  in wiz_clock_init()
1082 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);  in wiz_clock_init()
1085 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);  in wiz_clock_init()
1104 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);  in wiz_clock_init()
1106 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);  in wiz_clock_init()
1119 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);  in wiz_clock_init()
1121 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);  in wiz_clock_init()
1191 		ret = regmap_field_write(wiz->phy_reset_n, false);  in wiz_phy_reset_assert()
1195 	ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);  in wiz_phy_reset_assert()
1204 			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);  in wiz_phy_fullrt_div()
1209 			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);  in wiz_phy_fullrt_div()
1230 			regmap_field_write(wiz->typec_ln10_swap, 1);  in wiz_phy_reset_deassert()
1232 			regmap_field_write(wiz->typec_ln10_swap, 0);  in wiz_phy_reset_deassert()
1236 		ret = regmap_field_write(wiz->phy_reset_n, true);  in wiz_phy_reset_deassert()
1245 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);  in wiz_phy_reset_deassert()
1247 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);  in wiz_phy_reset_deassert()
1486 		regmap_field_write(wiz->sup_legacy_clk_override, 1);  in wiz_probe()