334 struct wiz {  struct
377 static int wiz_reset(struct wiz *wiz)  in wiz_reset()  argument
381 	ret = regmap_field_write(wiz->por_en, 0x1);  in wiz_reset()
387 	ret = regmap_field_write(wiz->por_en, 0x0);  in wiz_reset()
394 static int wiz_p_mac_div_sel(struct wiz *wiz)  in wiz_p_mac_div_sel()  argument
396 	u32 num_lanes = wiz->num_lanes;  in wiz_p_mac_div_sel()
401 		if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||  in wiz_p_mac_div_sel()
402 		    wiz->lane_phy_type[i] == PHY_TYPE_QSGMII ||  in wiz_p_mac_div_sel()
403 		    wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {  in wiz_p_mac_div_sel()
404 			ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);  in wiz_p_mac_div_sel()
408 			ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);  in wiz_p_mac_div_sel()
417 static int wiz_mode_select(struct wiz *wiz)  in wiz_mode_select()  argument
419 	u32 num_lanes = wiz->num_lanes;  in wiz_mode_select()
425 		if (wiz->lane_phy_type[i] == PHY_TYPE_DP)  in wiz_mode_select()
427 		else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII)  in wiz_mode_select()
432 		if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {  in wiz_mode_select()
433 			ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);  in wiz_mode_select()
434 			ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);  in wiz_mode_select()
435 			ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);  in wiz_mode_select()
439 		ret = regmap_field_write(wiz->p_standard_mode[i], mode);  in wiz_mode_select()
447 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)  in wiz_init_raw_interface()  argument
449 	u32 num_lanes = wiz->num_lanes;  in wiz_init_raw_interface()
454 		ret = regmap_field_write(wiz->p_align[i], enable);  in wiz_init_raw_interface()
458 		ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);  in wiz_init_raw_interface()
466 static int wiz_init(struct wiz *wiz)  in wiz_init()  argument
468 	struct device *dev = wiz->dev;  in wiz_init()
471 	ret = wiz_reset(wiz);  in wiz_init()
473 		dev_err(dev, "WIZ reset failed\n");  in wiz_init()
477 	ret = wiz_mode_select(wiz);  in wiz_init()
479 		dev_err(dev, "WIZ mode select failed\n");  in wiz_init()
483 	ret = wiz_p_mac_div_sel(wiz);  in wiz_init()
489 	ret = wiz_init_raw_interface(wiz, true);  in wiz_init()
491 		dev_err(dev, "WIZ interface initialization failed\n");  in wiz_init()
498 static int wiz_regfield_init(struct wiz *wiz)  in wiz_regfield_init()  argument
500 	struct regmap *regmap = wiz->regmap;  in wiz_regfield_init()
501 	struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */  in wiz_regfield_init()
502 	int num_lanes = wiz->num_lanes;  in wiz_regfield_init()
503 	struct device *dev = wiz->dev;  in wiz_regfield_init()
504 	const struct wiz_data *data = wiz->data;  in wiz_regfield_init()
507 	wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);  in wiz_regfield_init()
508 	if (IS_ERR(wiz->por_en)) {  in wiz_regfield_init()
510 		return PTR_ERR(wiz->por_en);  in wiz_regfield_init()
513 	wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
515 	if (IS_ERR(wiz->phy_reset_n)) {  in wiz_regfield_init()
517 		return PTR_ERR(wiz->phy_reset_n);  in wiz_regfield_init()
520 	wiz->pma_cmn_refclk_int_mode =  in wiz_regfield_init()
522 	if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {  in wiz_regfield_init()
524 		return PTR_ERR(wiz->pma_cmn_refclk_int_mode);  in wiz_regfield_init()
527 	wiz->pma_cmn_refclk_mode =  in wiz_regfield_init()
529 	if (IS_ERR(wiz->pma_cmn_refclk_mode)) {  in wiz_regfield_init()
531 		return PTR_ERR(wiz->pma_cmn_refclk_mode);  in wiz_regfield_init()
534 	wiz->div_sel_field[CMN_REFCLK_DIG_DIV] =  in wiz_regfield_init()
536 	if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) {  in wiz_regfield_init()
538 		return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);  in wiz_regfield_init()
542 		wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =  in wiz_regfield_init()
545 		if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {  in wiz_regfield_init()
547 			return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);  in wiz_regfield_init()
551 	if (wiz->scm_regmap) {  in wiz_regfield_init()
552 		scm_regmap = wiz->scm_regmap;  in wiz_regfield_init()
553 		wiz->sup_legacy_clk_override =  in wiz_regfield_init()
555 		if (IS_ERR(wiz->sup_legacy_clk_override)) {  in wiz_regfield_init()
557 			return PTR_ERR(wiz->sup_legacy_clk_override);  in wiz_regfield_init()
561 	wiz->mux_sel_field[PLL0_REFCLK] =  in wiz_regfield_init()
563 	if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {  in wiz_regfield_init()
565 		return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);  in wiz_regfield_init()
568 	wiz->mux_sel_field[PLL1_REFCLK] =  in wiz_regfield_init()
570 	if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {  in wiz_regfield_init()
572 		return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);  in wiz_regfield_init()
575 	wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap,  in wiz_regfield_init()
577 	if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {  in wiz_regfield_init()
579 		return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);  in wiz_regfield_init()
583 		wiz->pma_cmn_refclk1_int_mode =  in wiz_regfield_init()
585 		if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {  in wiz_regfield_init()
587 			return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);  in wiz_regfield_init()
592 		wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
594 		if (IS_ERR(wiz->p_enable[i])) {  in wiz_regfield_init()
596 			return PTR_ERR(wiz->p_enable[i]);  in wiz_regfield_init()
599 		wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
601 		if (IS_ERR(wiz->p_align[i])) {  in wiz_regfield_init()
603 			return PTR_ERR(wiz->p_align[i]);  in wiz_regfield_init()
606 		wiz->p_raw_auto_start[i] =  in wiz_regfield_init()
608 		if (IS_ERR(wiz->p_raw_auto_start[i])) {  in wiz_regfield_init()
611 			return PTR_ERR(wiz->p_raw_auto_start[i]);  in wiz_regfield_init()
614 		wiz->p_standard_mode[i] =  in wiz_regfield_init()
616 		if (IS_ERR(wiz->p_standard_mode[i])) {  in wiz_regfield_init()
619 			return PTR_ERR(wiz->p_standard_mode[i]);  in wiz_regfield_init()
622 		wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);  in wiz_regfield_init()
623 		if (IS_ERR(wiz->p0_fullrt_div[i])) {  in wiz_regfield_init()
625 			return PTR_ERR(wiz->p0_fullrt_div[i]);  in wiz_regfield_init()
628 		wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]);  in wiz_regfield_init()
629 		if (IS_ERR(wiz->p0_mac_src_sel[i])) {  in wiz_regfield_init()
631 			return PTR_ERR(wiz->p0_mac_src_sel[i]);  in wiz_regfield_init()
634 		wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]);  in wiz_regfield_init()
635 		if (IS_ERR(wiz->p0_rxfclk_sel[i])) {  in wiz_regfield_init()
637 			return PTR_ERR(wiz->p0_rxfclk_sel[i]);  in wiz_regfield_init()
640 		wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]);  in wiz_regfield_init()
641 		if (IS_ERR(wiz->p0_refclk_sel[i])) {  in wiz_regfield_init()
643 			return PTR_ERR(wiz->p0_refclk_sel[i]);  in wiz_regfield_init()
646 		wiz->p_mac_div_sel0[i] =  in wiz_regfield_init()
648 		if (IS_ERR(wiz->p_mac_div_sel0[i])) {  in wiz_regfield_init()
651 			return PTR_ERR(wiz->p_mac_div_sel0[i]);  in wiz_regfield_init()
654 		wiz->p_mac_div_sel1[i] =  in wiz_regfield_init()
656 		if (IS_ERR(wiz->p_mac_div_sel1[i])) {  in wiz_regfield_init()
659 			return PTR_ERR(wiz->p_mac_div_sel1[i]);  in wiz_regfield_init()
663 	wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
665 	if (IS_ERR(wiz->typec_ln10_swap)) {  in wiz_regfield_init()
667 		return PTR_ERR(wiz->typec_ln10_swap);  in wiz_regfield_init()
670 	wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);  in wiz_regfield_init()
671 	if (IS_ERR(wiz->phy_en_refclk)) {  in wiz_regfield_init()
673 		return PTR_ERR(wiz->phy_en_refclk);  in wiz_regfield_init()
714 static int wiz_phy_en_refclk_register(struct wiz *wiz)  in wiz_phy_en_refclk_register()  argument
717 	struct device *dev = wiz->dev;  in wiz_phy_en_refclk_register()
741 	wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;  in wiz_phy_en_refclk_register()
751 	wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;  in wiz_phy_en_refclk_register()
781 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,  in wiz_mux_clk_register()  argument
784 	struct device *dev = wiz->dev;  in wiz_mux_clk_register()
804 		clk = wiz->input_clks[mux_sel->parents[i]];  in wiz_mux_clk_register()
834 	wiz->output_clks[clk_index] = clk;  in wiz_mux_clk_register()
842 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,  in wiz_mux_of_clk_register()  argument
845 	struct device *dev = wiz->dev;  in wiz_mux_of_clk_register()
937 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,  in wiz_div_clk_register()  argument
941 	struct device *dev = wiz->dev;  in wiz_div_clk_register()
985 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)  in wiz_clock_cleanup()  argument
987 	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_cleanup()
988 	struct device *dev = wiz->dev;  in wiz_clock_cleanup()
992 	switch (wiz->type) {  in wiz_clock_cleanup()
1007 	for (i = 0; i < wiz->clk_div_sel_num; i++) {  in wiz_clock_cleanup()
1013 	of_clk_del_provider(wiz->dev->of_node);  in wiz_clock_cleanup()
1016 static int wiz_clock_register(struct wiz *wiz)  in wiz_clock_register()  argument
1018 	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_register()
1019 	struct device *dev = wiz->dev;  in wiz_clock_register()
1027 		ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);  in wiz_clock_register()
1034 	ret = wiz_phy_en_refclk_register(wiz);  in wiz_clock_register()
1040 	wiz->clk_data.clks = wiz->output_clks;  in wiz_clock_register()
1041 	wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;  in wiz_clock_register()
1042 	ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);  in wiz_clock_register()
1049 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)  in wiz_clock_init()  argument
1051 	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_init()
1052 	struct device *dev = wiz->dev;  in wiz_clock_init()
1066 	wiz->input_clks[WIZ_CORE_REFCLK] = clk;  in wiz_clock_init()
1070 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);  in wiz_clock_init()
1072 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);  in wiz_clock_init()
1074 	switch (wiz->type) {  in wiz_clock_init()
1079 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);  in wiz_clock_init()
1082 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);  in wiz_clock_init()
1085 			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);  in wiz_clock_init()
1093 	if (wiz->data->pma_cmn_refclk1_int_mode) {  in wiz_clock_init()
1100 		wiz->input_clks[WIZ_CORE_REFCLK1] = clk;  in wiz_clock_init()
1104 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);  in wiz_clock_init()
1106 			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);  in wiz_clock_init()
1115 	wiz->input_clks[WIZ_EXT_REFCLK] = clk;  in wiz_clock_init()
1119 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);  in wiz_clock_init()
1121 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);  in wiz_clock_init()
1123 	switch (wiz->type) {  in wiz_clock_init()
1126 		ret = wiz_clock_register(wiz);  in wiz_clock_init()
1128 			dev_err(dev, "Failed to register wiz clocks\n");  in wiz_clock_init()
1143 		ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],  in wiz_clock_init()
1155 	for (i = 0; i < wiz->clk_div_sel_num; i++) {  in wiz_clock_init()
1164 		ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i],  in wiz_clock_init()
1178 	wiz_clock_cleanup(wiz, node);  in wiz_clock_init()
1187 	struct wiz *wiz = dev_get_drvdata(dev);  in wiz_phy_reset_assert()  local
1191 		ret = regmap_field_write(wiz->phy_reset_n, false);  in wiz_phy_reset_assert()
1195 	ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);  in wiz_phy_reset_assert()
1199 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)  in wiz_phy_fullrt_div()  argument
1201 	switch (wiz->type) {  in wiz_phy_fullrt_div()
1203 		if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)  in wiz_phy_fullrt_div()
1204 			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);  in wiz_phy_fullrt_div()
1208 		if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)  in wiz_phy_fullrt_div()
1209 			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);  in wiz_phy_fullrt_div()
1221 	struct wiz *wiz = dev_get_drvdata(dev);  in wiz_phy_reset_deassert()  local
1225 	if (id == 0 && wiz->gpio_typec_dir) {  in wiz_phy_reset_deassert()
1226 		if (wiz->typec_dir_delay)  in wiz_phy_reset_deassert()
1227 			msleep_interruptible(wiz->typec_dir_delay);  in wiz_phy_reset_deassert()
1229 		if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))  in wiz_phy_reset_deassert()
1230 			regmap_field_write(wiz->typec_ln10_swap, 1);  in wiz_phy_reset_deassert()
1232 			regmap_field_write(wiz->typec_ln10_swap, 0);  in wiz_phy_reset_deassert()
1236 		ret = regmap_field_write(wiz->phy_reset_n, true);  in wiz_phy_reset_deassert()
1240 	ret = wiz_phy_fullrt_div(wiz, id - 1);  in wiz_phy_reset_deassert()
1244 	if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)  in wiz_phy_reset_deassert()
1245 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);  in wiz_phy_reset_deassert()
1247 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);  in wiz_phy_reset_deassert()
1304 		.compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
1307 		.compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
1310 		.compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
1313 		.compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
1319 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)  in wiz_get_lane_phy_types()  argument
1352 			wiz->lane_phy_type[i] = phy_type;  in wiz_get_lane_phy_types()
1369 	struct wiz *wiz;  in wiz_probe()  local
1374 	wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);  in wiz_probe()
1375 	if (!wiz)  in wiz_probe()
1384 	wiz->data = data;  in wiz_probe()
1385 	wiz->type = data->type;  in wiz_probe()
1412 	wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm");  in wiz_probe()
1413 	if (IS_ERR(wiz->scm_regmap)) {  in wiz_probe()
1414 		if (wiz->type == J7200_WIZ_10G) {  in wiz_probe()
1420 		wiz->scm_regmap = NULL;  in wiz_probe()
1435 	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",  in wiz_probe()
1437 	if (IS_ERR(wiz->gpio_typec_dir)) {  in wiz_probe()
1438 		ret = PTR_ERR(wiz->gpio_typec_dir);  in wiz_probe()
1445 	if (wiz->gpio_typec_dir) {  in wiz_probe()
1447 					   &wiz->typec_dir_delay);  in wiz_probe()
1455 			wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;  in wiz_probe()
1457 		if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||  in wiz_probe()
1458 		    wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {  in wiz_probe()
1465 	ret = wiz_get_lane_phy_types(dev, wiz);  in wiz_probe()
1469 	wiz->dev = dev;  in wiz_probe()
1470 	wiz->regmap = regmap;  in wiz_probe()
1471 	wiz->num_lanes = num_lanes;  in wiz_probe()
1472 	wiz->clk_mux_sel = data->clk_mux_sel;  in wiz_probe()
1473 	wiz->clk_div_sel = clk_div_sel;  in wiz_probe()
1474 	wiz->clk_div_sel_num = data->clk_div_sel_num;  in wiz_probe()
1476 	platform_set_drvdata(pdev, wiz);  in wiz_probe()
1478 	ret = wiz_regfield_init(wiz);  in wiz_probe()
1485 	if (wiz->scm_regmap)  in wiz_probe()
1486 		regmap_field_write(wiz->sup_legacy_clk_override, 1);  in wiz_probe()
1488 	phy_reset_dev = &wiz->wiz_phy_reset_dev;  in wiz_probe()
1509 	ret = wiz_clock_init(wiz, node);  in wiz_probe()
1515 	for (i = 0; i < wiz->num_lanes; i++) {  in wiz_probe()
1516 		regmap_field_read(wiz->p_enable[i], &val);  in wiz_probe()
1524 		ret = wiz_init(wiz);  in wiz_probe()
1526 			dev_err(dev, "WIZ initialization failed\n");  in wiz_probe()
1537 	wiz->serdes_pdev = serdes_pdev;  in wiz_probe()
1543 	wiz_clock_cleanup(wiz, node);  in wiz_probe()
1560 	struct wiz *wiz;  in wiz_remove()  local
1562 	wiz = dev_get_drvdata(dev);  in wiz_remove()
1563 	serdes_pdev = wiz->serdes_pdev;  in wiz_remove()
1566 	wiz_clock_cleanup(wiz, node);  in wiz_remove()
1577 		.name	= "wiz",
1584 MODULE_DESCRIPTION("TI J721E WIZ driver");