Lines Matching +full:- +full:dig +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
13 #include <linux/clk-provider.h>
25 #include <linux/reset-controller.h>
111 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
112 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
113 [TI_WIZ_REFCLK_DIG] = "refclk-dig",
114 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
236 .node_name = "pll0-refclk",
240 .node_name = "pll1-refclk",
244 .node_name = "refclk-dig",
257 .node_name = "pll0-refclk",
263 .node_name = "pll1-refclk",
269 .node_name = "refclk-dig",
278 .node_name = "pll0-refclk",
284 .node_name = "pll1-refclk",
290 .node_name = "refclk-dig",
295 { .val = 0, .div = 1, },
296 { .val = 1, .div = 2, },
297 { .val = 2, .div = 4, },
298 { .val = 3, .div = 8, },
305 .node_name = "cmn-refclk-dig-div",
309 .node_name = "cmn-refclk1-dig-div",
381 ret = regmap_field_write(wiz->por_en, 0x1); in wiz_reset()
387 ret = regmap_field_write(wiz->por_en, 0x0); in wiz_reset()
396 u32 num_lanes = wiz->num_lanes; in wiz_p_mac_div_sel()
401 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || in wiz_p_mac_div_sel()
402 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || in wiz_p_mac_div_sel()
403 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { in wiz_p_mac_div_sel()
404 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); in wiz_p_mac_div_sel()
408 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); in wiz_p_mac_div_sel()
419 u32 num_lanes = wiz->num_lanes; in wiz_mode_select()
425 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) in wiz_mode_select()
427 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) in wiz_mode_select()
432 if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { in wiz_mode_select()
433 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); in wiz_mode_select()
434 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); in wiz_mode_select()
435 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); in wiz_mode_select()
439 ret = regmap_field_write(wiz->p_standard_mode[i], mode); in wiz_mode_select()
449 u32 num_lanes = wiz->num_lanes; in wiz_init_raw_interface()
454 ret = regmap_field_write(wiz->p_align[i], enable); in wiz_init_raw_interface()
458 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); in wiz_init_raw_interface()
468 struct device *dev = wiz->dev; in wiz_init()
485 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); in wiz_init()
500 struct regmap *regmap = wiz->regmap; in wiz_regfield_init()
501 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */ in wiz_regfield_init()
502 int num_lanes = wiz->num_lanes; in wiz_regfield_init()
503 struct device *dev = wiz->dev; in wiz_regfield_init()
504 const struct wiz_data *data = wiz->data; in wiz_regfield_init()
507 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); in wiz_regfield_init()
508 if (IS_ERR(wiz->por_en)) { in wiz_regfield_init()
510 return PTR_ERR(wiz->por_en); in wiz_regfield_init()
513 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
515 if (IS_ERR(wiz->phy_reset_n)) { in wiz_regfield_init()
517 return PTR_ERR(wiz->phy_reset_n); in wiz_regfield_init()
520 wiz->pma_cmn_refclk_int_mode = in wiz_regfield_init()
522 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { in wiz_regfield_init()
524 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); in wiz_regfield_init()
527 wiz->pma_cmn_refclk_mode = in wiz_regfield_init()
529 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { in wiz_regfield_init()
531 return PTR_ERR(wiz->pma_cmn_refclk_mode); in wiz_regfield_init()
534 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = in wiz_regfield_init()
536 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { in wiz_regfield_init()
538 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); in wiz_regfield_init()
541 if (data->pma_cmn_refclk1_dig_div) { in wiz_regfield_init()
542 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = in wiz_regfield_init()
544 *data->pma_cmn_refclk1_dig_div); in wiz_regfield_init()
545 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { in wiz_regfield_init()
547 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); in wiz_regfield_init()
551 if (wiz->scm_regmap) { in wiz_regfield_init()
552 scm_regmap = wiz->scm_regmap; in wiz_regfield_init()
553 wiz->sup_legacy_clk_override = in wiz_regfield_init()
555 if (IS_ERR(wiz->sup_legacy_clk_override)) { in wiz_regfield_init()
557 return PTR_ERR(wiz->sup_legacy_clk_override); in wiz_regfield_init()
561 wiz->mux_sel_field[PLL0_REFCLK] = in wiz_regfield_init()
562 devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel); in wiz_regfield_init()
563 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { in wiz_regfield_init()
565 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); in wiz_regfield_init()
568 wiz->mux_sel_field[PLL1_REFCLK] = in wiz_regfield_init()
569 devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel); in wiz_regfield_init()
570 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { in wiz_regfield_init()
572 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); in wiz_regfield_init()
575 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap, in wiz_regfield_init()
576 *data->refclk_dig_sel); in wiz_regfield_init()
577 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { in wiz_regfield_init()
579 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); in wiz_regfield_init()
582 if (data->pma_cmn_refclk1_int_mode) { in wiz_regfield_init()
583 wiz->pma_cmn_refclk1_int_mode = in wiz_regfield_init()
584 devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode); in wiz_regfield_init()
585 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { in wiz_regfield_init()
587 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); in wiz_regfield_init()
592 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
594 if (IS_ERR(wiz->p_enable[i])) { in wiz_regfield_init()
596 return PTR_ERR(wiz->p_enable[i]); in wiz_regfield_init()
599 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
601 if (IS_ERR(wiz->p_align[i])) { in wiz_regfield_init()
603 return PTR_ERR(wiz->p_align[i]); in wiz_regfield_init()
606 wiz->p_raw_auto_start[i] = in wiz_regfield_init()
608 if (IS_ERR(wiz->p_raw_auto_start[i])) { in wiz_regfield_init()
611 return PTR_ERR(wiz->p_raw_auto_start[i]); in wiz_regfield_init()
614 wiz->p_standard_mode[i] = in wiz_regfield_init()
616 if (IS_ERR(wiz->p_standard_mode[i])) { in wiz_regfield_init()
619 return PTR_ERR(wiz->p_standard_mode[i]); in wiz_regfield_init()
622 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); in wiz_regfield_init()
623 if (IS_ERR(wiz->p0_fullrt_div[i])) { in wiz_regfield_init()
625 return PTR_ERR(wiz->p0_fullrt_div[i]); in wiz_regfield_init()
628 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); in wiz_regfield_init()
629 if (IS_ERR(wiz->p0_mac_src_sel[i])) { in wiz_regfield_init()
631 return PTR_ERR(wiz->p0_mac_src_sel[i]); in wiz_regfield_init()
634 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); in wiz_regfield_init()
635 if (IS_ERR(wiz->p0_rxfclk_sel[i])) { in wiz_regfield_init()
637 return PTR_ERR(wiz->p0_rxfclk_sel[i]); in wiz_regfield_init()
640 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); in wiz_regfield_init()
641 if (IS_ERR(wiz->p0_refclk_sel[i])) { in wiz_regfield_init()
643 return PTR_ERR(wiz->p0_refclk_sel[i]); in wiz_regfield_init()
646 wiz->p_mac_div_sel0[i] = in wiz_regfield_init()
648 if (IS_ERR(wiz->p_mac_div_sel0[i])) { in wiz_regfield_init()
651 return PTR_ERR(wiz->p_mac_div_sel0[i]); in wiz_regfield_init()
654 wiz->p_mac_div_sel1[i] = in wiz_regfield_init()
656 if (IS_ERR(wiz->p_mac_div_sel1[i])) { in wiz_regfield_init()
659 return PTR_ERR(wiz->p_mac_div_sel1[i]); in wiz_regfield_init()
663 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
665 if (IS_ERR(wiz->typec_ln10_swap)) { in wiz_regfield_init()
667 return PTR_ERR(wiz->typec_ln10_swap); in wiz_regfield_init()
670 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); in wiz_regfield_init()
671 if (IS_ERR(wiz->phy_en_refclk)) { in wiz_regfield_init()
673 return PTR_ERR(wiz->phy_en_refclk); in wiz_regfield_init()
682 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; in wiz_phy_en_refclk_enable()
692 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; in wiz_phy_en_refclk_disable()
700 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; in wiz_phy_en_refclk_is_enabled()
717 struct device *dev = wiz->dev; in wiz_phy_en_refclk_register()
725 return -ENOMEM; in wiz_phy_en_refclk_register()
727 init = &wiz_phy_en_refclk->clk_data; in wiz_phy_en_refclk_register()
729 init->ops = &wiz_phy_en_refclk_ops; in wiz_phy_en_refclk_register()
730 init->flags = 0; in wiz_phy_en_refclk_register()
736 return -ENOMEM; in wiz_phy_en_refclk_register()
739 init->name = clk_name; in wiz_phy_en_refclk_register()
741 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; in wiz_phy_en_refclk_register()
742 wiz_phy_en_refclk->hw.init = init; in wiz_phy_en_refclk_register()
744 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); in wiz_phy_en_refclk_register()
751 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; in wiz_phy_en_refclk_register()
759 struct regmap_field *field = mux->field; in wiz_clk_mux_get_parent()
763 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); in wiz_clk_mux_get_parent()
769 struct regmap_field *field = mux->field; in wiz_clk_mux_set_parent()
772 val = mux->table[index]; in wiz_clk_mux_set_parent()
784 struct device *dev = wiz->dev; in wiz_mux_clk_register()
795 return -ENOMEM; in wiz_mux_clk_register()
797 num_parents = mux_sel->num_parents; in wiz_mux_clk_register()
801 return -ENOMEM; in wiz_mux_clk_register()
804 clk = wiz->input_clks[mux_sel->parents[i]]; in wiz_mux_clk_register()
808 ret = -EINVAL; in wiz_mux_clk_register()
816 init = &mux->clk_data; in wiz_mux_clk_register()
818 init->ops = &wiz_clk_mux_ops; in wiz_mux_clk_register()
819 init->flags = CLK_SET_RATE_NO_REPARENT; in wiz_mux_clk_register()
820 init->parent_names = parent_names; in wiz_mux_clk_register()
821 init->num_parents = num_parents; in wiz_mux_clk_register()
822 init->name = clk_name; in wiz_mux_clk_register()
824 mux->field = field; in wiz_mux_clk_register()
825 mux->table = mux_sel->table; in wiz_mux_clk_register()
826 mux->hw.init = init; in wiz_mux_clk_register()
828 clk = devm_clk_register(dev, &mux->hw); in wiz_mux_clk_register()
834 wiz->output_clks[clk_index] = clk; in wiz_mux_clk_register()
845 struct device *dev = wiz->dev; in wiz_mux_of_clk_register()
856 return -ENOMEM; in wiz_mux_of_clk_register()
861 return -EINVAL; in wiz_mux_of_clk_register()
867 return -ENOMEM; in wiz_mux_of_clk_register()
872 node->name); in wiz_mux_of_clk_register()
874 init = &mux->clk_data; in wiz_mux_of_clk_register()
876 init->ops = &wiz_clk_mux_ops; in wiz_mux_of_clk_register()
877 init->flags = CLK_SET_RATE_NO_REPARENT; in wiz_mux_of_clk_register()
878 init->parent_names = parent_names; in wiz_mux_of_clk_register()
879 init->num_parents = num_parents; in wiz_mux_of_clk_register()
880 init->name = clk_name; in wiz_mux_of_clk_register()
882 mux->field = field; in wiz_mux_of_clk_register()
883 mux->table = table; in wiz_mux_of_clk_register()
884 mux->hw.init = init; in wiz_mux_of_clk_register()
886 clk = devm_clk_register(dev, &mux->hw); in wiz_mux_of_clk_register()
900 struct wiz_clk_divider *div = to_wiz_clk_div(hw); in wiz_clk_div_recalc_rate() local
901 struct regmap_field *field = div->field; in wiz_clk_div_recalc_rate()
906 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); in wiz_clk_div_recalc_rate()
912 struct wiz_clk_divider *div = to_wiz_clk_div(hw); in wiz_clk_div_round_rate() local
914 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); in wiz_clk_div_round_rate()
920 struct wiz_clk_divider *div = to_wiz_clk_div(hw); in wiz_clk_div_set_rate() local
921 struct regmap_field *field = div->field; in wiz_clk_div_set_rate()
924 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); in wiz_clk_div_set_rate()
941 struct device *dev = wiz->dev; in wiz_div_clk_register()
942 struct wiz_clk_divider *div; in wiz_div_clk_register() local
949 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); in wiz_div_clk_register()
950 if (!div) in wiz_div_clk_register()
951 return -ENOMEM; in wiz_div_clk_register()
954 node->name); in wiz_div_clk_register()
958 return -ENOMEM; in wiz_div_clk_register()
962 init = &div->clk_data; in wiz_div_clk_register()
964 init->ops = &wiz_clk_div_ops; in wiz_div_clk_register()
965 init->flags = 0; in wiz_div_clk_register()
966 init->parent_names = parent_names; in wiz_div_clk_register()
967 init->num_parents = 1; in wiz_div_clk_register()
968 init->name = clk_name; in wiz_div_clk_register()
970 div->field = field; in wiz_div_clk_register()
971 div->table = table; in wiz_div_clk_register()
972 div->hw.init = init; in wiz_div_clk_register()
974 clk = devm_clk_register(dev, &div->hw); in wiz_div_clk_register()
987 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_cleanup()
988 struct device *dev = wiz->dev; in wiz_clock_cleanup()
992 switch (wiz->type) { in wiz_clock_cleanup()
995 of_clk_del_provider(dev->of_node); in wiz_clock_cleanup()
1007 for (i = 0; i < wiz->clk_div_sel_num; i++) { in wiz_clock_cleanup()
1013 of_clk_del_provider(wiz->dev->of_node); in wiz_clock_cleanup()
1018 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_register()
1019 struct device *dev = wiz->dev; in wiz_clock_register()
1020 struct device_node *node = dev->of_node; in wiz_clock_register()
1027 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); in wiz_clock_register()
1036 dev_err(dev, "Failed to add phy-en-refclk\n"); in wiz_clock_register()
1040 wiz->clk_data.clks = wiz->output_clks; in wiz_clock_register()
1041 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; in wiz_clock_register()
1042 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); in wiz_clock_register()
1044 dev_err(dev, "Failed to add clock provider: %s\n", node->name); in wiz_clock_register()
1051 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_init()
1052 struct device *dev = wiz->dev; in wiz_clock_init()
1066 wiz->input_clks[WIZ_CORE_REFCLK] = clk; in wiz_clock_init()
1070 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); in wiz_clock_init()
1072 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); in wiz_clock_init()
1074 switch (wiz->type) { in wiz_clock_init()
1079 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); in wiz_clock_init()
1082 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); in wiz_clock_init()
1085 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); in wiz_clock_init()
1093 if (wiz->data->pma_cmn_refclk1_int_mode) { in wiz_clock_init()
1100 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; in wiz_clock_init()
1104 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); in wiz_clock_init()
1106 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); in wiz_clock_init()
1115 wiz->input_clks[WIZ_EXT_REFCLK] = clk; in wiz_clock_init()
1119 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); in wiz_clock_init()
1121 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); in wiz_clock_init()
1123 switch (wiz->type) { in wiz_clock_init()
1139 ret = -EINVAL; in wiz_clock_init()
1143 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], in wiz_clock_init()
1155 for (i = 0; i < wiz->clk_div_sel_num; i++) { in wiz_clock_init()
1160 ret = -EINVAL; in wiz_clock_init()
1164 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], in wiz_clock_init()
1186 struct device *dev = rcdev->dev; in wiz_phy_reset_assert()
1191 ret = regmap_field_write(wiz->phy_reset_n, false); in wiz_phy_reset_assert()
1195 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); in wiz_phy_reset_assert()
1201 switch (wiz->type) { in wiz_phy_fullrt_div()
1203 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) in wiz_phy_fullrt_div()
1204 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); in wiz_phy_fullrt_div()
1208 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) in wiz_phy_fullrt_div()
1209 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); in wiz_phy_fullrt_div()
1220 struct device *dev = rcdev->dev; in wiz_phy_reset_deassert()
1224 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ in wiz_phy_reset_deassert()
1225 if (id == 0 && wiz->gpio_typec_dir) { in wiz_phy_reset_deassert()
1226 if (wiz->typec_dir_delay) in wiz_phy_reset_deassert()
1227 msleep_interruptible(wiz->typec_dir_delay); in wiz_phy_reset_deassert()
1229 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) in wiz_phy_reset_deassert()
1230 regmap_field_write(wiz->typec_ln10_swap, 1); in wiz_phy_reset_deassert()
1232 regmap_field_write(wiz->typec_ln10_swap, 0); in wiz_phy_reset_deassert()
1236 ret = regmap_field_write(wiz->phy_reset_n, true); in wiz_phy_reset_deassert()
1240 ret = wiz_phy_fullrt_div(wiz, id - 1); in wiz_phy_reset_deassert()
1244 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) in wiz_phy_reset_deassert()
1245 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); in wiz_phy_reset_deassert()
1247 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); in wiz_phy_reset_deassert()
1304 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
1307 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
1310 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
1313 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
1323 serdes = of_get_child_by_name(dev->of_node, "serdes"); in wiz_get_lane_phy_types()
1325 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); in wiz_get_lane_phy_types()
1326 return -EINVAL; in wiz_get_lane_phy_types()
1342 __func__, subnode->name, ret); in wiz_get_lane_phy_types()
1345 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); in wiz_get_lane_phy_types()
1346 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); in wiz_get_lane_phy_types()
1348 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, in wiz_get_lane_phy_types()
1349 reg, reg + num_lanes - 1, phy_type); in wiz_get_lane_phy_types()
1352 wiz->lane_phy_type[i] = phy_type; in wiz_get_lane_phy_types()
1361 struct device *dev = &pdev->dev; in wiz_probe()
1362 struct device_node *node = dev->of_node; in wiz_probe()
1376 return -ENOMEM; in wiz_probe()
1381 return -EINVAL; in wiz_probe()
1384 wiz->data = data; in wiz_probe()
1385 wiz->type = data->type; in wiz_probe()
1390 return -ENODEV; in wiz_probe()
1401 ret = -ENOMEM; in wiz_probe()
1412 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm"); in wiz_probe()
1413 if (IS_ERR(wiz->scm_regmap)) { in wiz_probe()
1414 if (wiz->type == J7200_WIZ_10G) { in wiz_probe()
1416 ret = -ENODEV; in wiz_probe()
1420 wiz->scm_regmap = NULL; in wiz_probe()
1423 ret = of_property_read_u32(node, "num-lanes", &num_lanes); in wiz_probe()
1425 dev_err(dev, "Failed to read num-lanes property\n"); in wiz_probe()
1431 ret = -ENODEV; in wiz_probe()
1435 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", in wiz_probe()
1437 if (IS_ERR(wiz->gpio_typec_dir)) { in wiz_probe()
1438 ret = PTR_ERR(wiz->gpio_typec_dir); in wiz_probe()
1439 if (ret != -EPROBE_DEFER) in wiz_probe()
1440 dev_err(dev, "Failed to request typec-dir gpio: %d\n", in wiz_probe()
1445 if (wiz->gpio_typec_dir) { in wiz_probe()
1446 ret = of_property_read_u32(node, "typec-dir-debounce-ms", in wiz_probe()
1447 &wiz->typec_dir_delay); in wiz_probe()
1448 if (ret && ret != -EINVAL) { in wiz_probe()
1449 dev_err(dev, "Invalid typec-dir-debounce property\n"); in wiz_probe()
1453 /* use min. debounce from Type-C spec if not provided in DT */ in wiz_probe()
1454 if (ret == -EINVAL) in wiz_probe()
1455 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; in wiz_probe()
1457 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || in wiz_probe()
1458 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { in wiz_probe()
1459 ret = -EINVAL; in wiz_probe()
1460 dev_err(dev, "Invalid typec-dir-debounce property\n"); in wiz_probe()
1469 wiz->dev = dev; in wiz_probe()
1470 wiz->regmap = regmap; in wiz_probe()
1471 wiz->num_lanes = num_lanes; in wiz_probe()
1472 wiz->clk_mux_sel = data->clk_mux_sel; in wiz_probe()
1473 wiz->clk_div_sel = clk_div_sel; in wiz_probe()
1474 wiz->clk_div_sel_num = data->clk_div_sel_num; in wiz_probe()
1485 if (wiz->scm_regmap) in wiz_probe()
1486 regmap_field_write(wiz->sup_legacy_clk_override, 1); in wiz_probe()
1488 phy_reset_dev = &wiz->wiz_phy_reset_dev; in wiz_probe()
1489 phy_reset_dev->dev = dev; in wiz_probe()
1490 phy_reset_dev->ops = &wiz_phy_reset_ops, in wiz_probe()
1491 phy_reset_dev->owner = THIS_MODULE, in wiz_probe()
1492 phy_reset_dev->of_node = node; in wiz_probe()
1494 phy_reset_dev->nr_resets = num_lanes + 1; in wiz_probe()
1515 for (i = 0; i < wiz->num_lanes; i++) { in wiz_probe()
1516 regmap_field_read(wiz->p_enable[i], &val); in wiz_probe()
1534 ret = -ENOMEM; in wiz_probe()
1537 wiz->serdes_pdev = serdes_pdev; in wiz_probe()
1557 struct device *dev = &pdev->dev; in wiz_remove()
1558 struct device_node *node = dev->of_node; in wiz_remove()
1563 serdes_pdev = wiz->serdes_pdev; in wiz_remove()
1565 of_platform_device_destroy(&serdes_pdev->dev, NULL); in wiz_remove()