Lines Matching +full:xusb +full:- +full:padctl
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
24 #include "xusb.h"
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
432 to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl) in to_tegra210_xusb_padctl() argument
434 return container_of(padctl, struct tegra210_xusb_padctl, base); in to_tegra210_xusb_padctl()
451 for (map = tegra210_usb3_map; map->type; map++) { in tegra210_usb3_lane_map()
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
456 return map->port; in tegra210_usb3_lane_map()
460 return -EINVAL; in tegra210_usb3_lane_map()
463 /* must be called under padctl->lock */
464 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl) in tegra210_pex_uphy_enable() argument
466 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
472 if (pcie->enable) in tegra210_pex_uphy_enable()
475 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
482 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
486 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
491 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
502 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
504 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
506 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
508 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
510 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
512 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
520 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
522 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
529 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
531 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
533 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
535 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
538 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
542 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
544 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
546 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
548 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
553 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
561 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
565 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
567 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
572 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
580 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
584 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
586 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
591 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
599 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
603 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
606 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
619 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
623 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
625 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
630 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
638 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
642 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
644 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
648 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
650 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
652 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
654 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
656 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
658 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
665 pcie->enable = true; in tegra210_pex_uphy_enable()
667 for (i = 0; i < padctl->pcie->soc->num_lanes; i++) { in tegra210_pex_uphy_enable()
668 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pex_uphy_enable()
670 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pex_uphy_enable()
676 reset_control_assert(pcie->rst); in tegra210_pex_uphy_enable()
678 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_enable()
682 static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl) in tegra210_pex_uphy_disable() argument
684 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_disable()
688 if (WARN_ON(!pcie->enable)) in tegra210_pex_uphy_disable()
691 pcie->enable = false; in tegra210_pex_uphy_disable()
693 for (i = 0; i < padctl->pcie->soc->num_lanes; i++) { in tegra210_pex_uphy_disable()
694 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pex_uphy_disable()
696 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pex_uphy_disable()
699 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_disable()
702 /* must be called under padctl->lock */
703 static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl) in tegra210_sata_uphy_enable() argument
705 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_enable()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable()
713 if (sata->enable) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
724 err = clk_prepare_enable(sata->pll); in tegra210_sata_uphy_enable()
728 err = reset_control_deassert(sata->rst); in tegra210_sata_uphy_enable()
732 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
737 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
739 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
744 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
746 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
748 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
750 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
752 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
754 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
756 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
758 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
773 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
775 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
788 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
790 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
792 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
794 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
797 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
801 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
803 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
805 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
807 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
812 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
820 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
824 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
826 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
831 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
839 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
843 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
845 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
850 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
858 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
862 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
865 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
870 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
878 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
882 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
884 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
889 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
897 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
901 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
903 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
907 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
909 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
911 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
913 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
915 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
917 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
924 sata->enable = true; in tegra210_sata_uphy_enable()
926 for (i = 0; i < padctl->sata->soc->num_lanes; i++) { in tegra210_sata_uphy_enable()
927 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_uphy_enable()
929 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_uphy_enable()
935 reset_control_assert(sata->rst); in tegra210_sata_uphy_enable()
937 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_enable()
941 static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl) in tegra210_sata_uphy_disable() argument
943 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_disable()
947 if (WARN_ON(!sata->enable)) in tegra210_sata_uphy_disable()
950 sata->enable = false; in tegra210_sata_uphy_disable()
952 for (i = 0; i < padctl->sata->soc->num_lanes; i++) { in tegra210_sata_uphy_disable()
953 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_uphy_disable()
955 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_uphy_disable()
958 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_disable()
961 static void tegra210_aux_mux_lp0_clamp_disable(struct tegra_xusb_padctl *padctl) in tegra210_aux_mux_lp0_clamp_disable() argument
965 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
967 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
971 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
973 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
977 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
979 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_disable()
982 static void tegra210_aux_mux_lp0_clamp_enable(struct tegra_xusb_padctl *padctl) in tegra210_aux_mux_lp0_clamp_enable() argument
986 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
988 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
992 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
994 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
998 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
1000 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_aux_mux_lp0_clamp_enable()
1003 static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl) in tegra210_uphy_init() argument
1005 if (padctl->pcie) in tegra210_uphy_init()
1006 tegra210_pex_uphy_enable(padctl); in tegra210_uphy_init()
1008 if (padctl->sata) in tegra210_uphy_init()
1009 tegra210_sata_uphy_enable(padctl); in tegra210_uphy_init()
1014 dev_dbg(padctl->dev, "PLLE is already in HW control\n"); in tegra210_uphy_init()
1016 tegra210_aux_mux_lp0_clamp_disable(padctl); in tegra210_uphy_init()
1022 tegra210_uphy_deinit(struct tegra_xusb_padctl *padctl) in tegra210_uphy_deinit() argument
1024 tegra210_aux_mux_lp0_clamp_enable(padctl); in tegra210_uphy_deinit()
1026 if (padctl->sata) in tegra210_uphy_deinit()
1027 tegra210_sata_uphy_disable(padctl); in tegra210_uphy_deinit()
1029 if (padctl->pcie) in tegra210_uphy_deinit()
1030 tegra210_pex_uphy_disable(padctl); in tegra210_uphy_deinit()
1033 static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl, in tegra210_hsic_set_idle() argument
1038 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
1053 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk() local
1063 struct device *dev = padctl->dev; in tegra210_usb3_enable_phy_sleepwalk()
1068 return -EINVAL; in tegra210_usb3_enable_phy_sleepwalk()
1071 mutex_lock(&padctl->lock); in tegra210_usb3_enable_phy_sleepwalk()
1073 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_enable_phy_sleepwalk()
1075 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_enable_phy_sleepwalk()
1079 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_enable_phy_sleepwalk()
1081 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_enable_phy_sleepwalk()
1085 mutex_unlock(&padctl->lock); in tegra210_usb3_enable_phy_sleepwalk()
1092 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_disable_phy_sleepwalk() local
1094 struct device *dev = padctl->dev; in tegra210_usb3_disable_phy_sleepwalk()
1099 return -EINVAL; in tegra210_usb3_disable_phy_sleepwalk()
1102 mutex_lock(&padctl->lock); in tegra210_usb3_disable_phy_sleepwalk()
1104 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_disable_phy_sleepwalk()
1106 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_disable_phy_sleepwalk()
1110 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_disable_phy_sleepwalk()
1112 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_disable_phy_sleepwalk()
1114 mutex_unlock(&padctl->lock); in tegra210_usb3_disable_phy_sleepwalk()
1121 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_wake() local
1123 struct device *dev = padctl->dev; in tegra210_usb3_enable_phy_wake()
1128 return -EINVAL; in tegra210_usb3_enable_phy_wake()
1131 mutex_lock(&padctl->lock); in tegra210_usb3_enable_phy_wake()
1133 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_enable_phy_wake()
1136 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_enable_phy_wake()
1140 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_enable_phy_wake()
1143 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_enable_phy_wake()
1145 mutex_unlock(&padctl->lock); in tegra210_usb3_enable_phy_wake()
1152 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_disable_phy_wake() local
1154 struct device *dev = padctl->dev; in tegra210_usb3_disable_phy_wake()
1159 return -EINVAL; in tegra210_usb3_disable_phy_wake()
1162 mutex_lock(&padctl->lock); in tegra210_usb3_disable_phy_wake()
1164 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_disable_phy_wake()
1167 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_disable_phy_wake()
1171 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_disable_phy_wake()
1174 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_disable_phy_wake()
1176 mutex_unlock(&padctl->lock); in tegra210_usb3_disable_phy_wake()
1183 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_phy_remote_wake_detected() local
1190 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_usb3_phy_remote_wake_detected()
1199 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_utmi_enable_phy_wake() local
1200 unsigned int index = lane->index; in tegra210_utmi_enable_phy_wake()
1203 mutex_lock(&padctl->lock); in tegra210_utmi_enable_phy_wake()
1205 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_enable_phy_wake()
1208 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_enable_phy_wake()
1212 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_enable_phy_wake()
1215 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_enable_phy_wake()
1217 mutex_unlock(&padctl->lock); in tegra210_utmi_enable_phy_wake()
1224 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_utmi_disable_phy_wake() local
1225 unsigned int index = lane->index; in tegra210_utmi_disable_phy_wake()
1228 mutex_lock(&padctl->lock); in tegra210_utmi_disable_phy_wake()
1230 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_disable_phy_wake()
1233 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_disable_phy_wake()
1237 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_disable_phy_wake()
1240 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_disable_phy_wake()
1242 mutex_unlock(&padctl->lock); in tegra210_utmi_disable_phy_wake()
1249 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_utmi_phy_remote_wake_detected() local
1250 unsigned int index = lane->index; in tegra210_utmi_phy_remote_wake_detected()
1253 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_utmi_phy_remote_wake_detected()
1263 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_enable_phy_wake() local
1264 unsigned int index = lane->index; in tegra210_hsic_enable_phy_wake()
1267 mutex_lock(&padctl->lock); in tegra210_hsic_enable_phy_wake()
1269 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_enable_phy_wake()
1272 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_enable_phy_wake()
1276 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_enable_phy_wake()
1279 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_enable_phy_wake()
1281 mutex_unlock(&padctl->lock); in tegra210_hsic_enable_phy_wake()
1288 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_disable_phy_wake() local
1289 unsigned int index = lane->index; in tegra210_hsic_disable_phy_wake()
1292 mutex_lock(&padctl->lock); in tegra210_hsic_disable_phy_wake()
1294 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_disable_phy_wake()
1297 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_disable_phy_wake()
1301 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_disable_phy_wake()
1304 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_disable_phy_wake()
1306 mutex_unlock(&padctl->lock); in tegra210_hsic_disable_phy_wake()
1313 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_remote_wake_detected() local
1314 unsigned int index = lane->index; in tegra210_hsic_phy_remote_wake_detected()
1317 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0); in tegra210_hsic_phy_remote_wake_detected()
1328 WARN(regmap_read(_priv->regmap, _offset, &value), "read %s failed\n", #_offset);\
1333 WARN(regmap_write(_priv->regmap, _offset, _value), "write %s failed\n", #_offset)
1338 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pmc_utmi_enable_phy_sleepwalk() local
1339 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1340 unsigned int port = lane->index; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1343 if (!priv->regmap) in tegra210_pmc_utmi_enable_phy_sleepwalk()
1344 return -EOPNOTSUPP; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1347 return -EINVAL; in tegra210_pmc_utmi_enable_phy_sleepwalk()
1349 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1353 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(port)); in tegra210_pmc_utmi_enable_phy_sleepwalk()
1431 /* program electrical parameters read from XUSB PADCTL */ in tegra210_pmc_utmi_enable_phy_sleepwalk()
1443 * Set up the pull-ups and pull-downs of the signals during the four in tegra210_pmc_utmi_enable_phy_sleepwalk()
1454 /* J state: D+/D- = high/low, K state: D+/D- = low/high */ in tegra210_pmc_utmi_enable_phy_sleepwalk()
1461 /* J state: D+/D- = low/high, K state: D+/D- = high/low */ in tegra210_pmc_utmi_enable_phy_sleepwalk()
1510 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pmc_utmi_disable_phy_sleepwalk() local
1511 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl); in tegra210_pmc_utmi_disable_phy_sleepwalk()
1512 unsigned int port = lane->index; in tegra210_pmc_utmi_disable_phy_sleepwalk()
1515 if (!priv->regmap) in tegra210_pmc_utmi_disable_phy_sleepwalk()
1516 return -EOPNOTSUPP; in tegra210_pmc_utmi_disable_phy_sleepwalk()
1527 /* switch the electric control of the USB2.0 pad to XUSB or USB2 */ in tegra210_pmc_utmi_disable_phy_sleepwalk()
1559 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pmc_hsic_enable_phy_sleepwalk() local
1560 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl); in tegra210_pmc_hsic_enable_phy_sleepwalk()
1563 if (!priv->regmap) in tegra210_pmc_hsic_enable_phy_sleepwalk()
1564 return -EOPNOTSUPP; in tegra210_pmc_hsic_enable_phy_sleepwalk()
1624 * Set up the pull-ups and pull-downs of the signals during the four in tegra210_pmc_hsic_enable_phy_sleepwalk()
1660 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pmc_hsic_disable_phy_sleepwalk() local
1661 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl); in tegra210_pmc_hsic_disable_phy_sleepwalk()
1664 if (!priv->regmap) in tegra210_pmc_hsic_disable_phy_sleepwalk()
1665 return -EOPNOTSUPP; in tegra210_pmc_hsic_disable_phy_sleepwalk()
1695 static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl, in tegra210_usb3_set_lfps_detect() argument
1702 port = tegra_xusb_find_port(padctl, "usb3", index); in tegra210_usb3_set_lfps_detect()
1704 return -ENODEV; in tegra210_usb3_set_lfps_detect()
1706 lane = port->lane; in tegra210_usb3_set_lfps_detect()
1708 if (lane->pad == padctl->pcie) in tegra210_usb3_set_lfps_detect()
1709 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index); in tegra210_usb3_set_lfps_detect()
1713 value = padctl_readl(padctl, offset); in tegra210_usb3_set_lfps_detect()
1727 padctl_writel(padctl, value, offset); in tegra210_usb3_set_lfps_detect()
1744 "xusb",
1749 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),
1750 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),
1751 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),
1752 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),
1764 return ERR_PTR(-ENOMEM); in tegra210_usb2_lane_probe()
1766 INIT_LIST_HEAD(&usb2->base.list); in tegra210_usb2_lane_probe()
1767 usb2->base.soc = &pad->soc->lanes[index]; in tegra210_usb2_lane_probe()
1768 usb2->base.index = index; in tegra210_usb2_lane_probe()
1769 usb2->base.pad = pad; in tegra210_usb2_lane_probe()
1770 usb2->base.np = np; in tegra210_usb2_lane_probe()
1772 err = tegra_xusb_lane_parse_dt(&usb2->base, np); in tegra210_usb2_lane_probe()
1778 return &usb2->base; in tegra210_usb2_lane_probe()
1801 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_init() local
1802 unsigned int index = lane->index; in tegra210_usb2_phy_init()
1807 port = tegra_xusb_find_usb2_port(padctl, index); in tegra210_usb2_phy_init()
1809 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index); in tegra210_usb2_phy_init()
1810 return -ENODEV; in tegra210_usb2_phy_init()
1813 if (port->supply && port->mode == USB_DR_MODE_HOST) { in tegra210_usb2_phy_init()
1814 err = regulator_enable(port->supply); in tegra210_usb2_phy_init()
1819 mutex_lock(&padctl->lock); in tegra210_usb2_phy_init()
1821 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
1826 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
1828 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_init()
1836 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_exit() local
1840 port = tegra_xusb_find_usb2_port(padctl, lane->index); in tegra210_usb2_phy_exit()
1842 dev_err(&phy->dev, "no port found for USB2 lane %u\n", lane->index); in tegra210_usb2_phy_exit()
1843 return -ENODEV; in tegra210_usb2_phy_exit()
1846 if (port->supply && port->mode == USB_DR_MODE_HOST) { in tegra210_usb2_phy_exit()
1847 err = regulator_disable(port->supply); in tegra210_usb2_phy_exit()
1855 static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, in tegra210_xusb_padctl_vbus_override() argument
1860 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear"); in tegra210_xusb_padctl_vbus_override()
1862 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_vbus_override()
1874 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_vbus_override()
1879 static int tegra210_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl, in tegra210_xusb_padctl_id_override() argument
1884 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear"); in tegra210_xusb_padctl_id_override()
1886 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1891 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1894 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1908 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1917 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_set_mode() local
1918 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl, in tegra210_usb2_phy_set_mode()
1919 lane->index); in tegra210_usb2_phy_set_mode()
1922 mutex_lock(&padctl->lock); in tegra210_usb2_phy_set_mode()
1924 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode); in tegra210_usb2_phy_set_mode()
1928 tegra210_xusb_padctl_id_override(padctl, true); in tegra210_usb2_phy_set_mode()
1930 err = regulator_enable(port->supply); in tegra210_usb2_phy_set_mode()
1932 tegra210_xusb_padctl_vbus_override(padctl, true); in tegra210_usb2_phy_set_mode()
1939 if (regulator_is_enabled(port->supply)) in tegra210_usb2_phy_set_mode()
1940 regulator_disable(port->supply); in tegra210_usb2_phy_set_mode()
1942 tegra210_xusb_padctl_id_override(padctl, false); in tegra210_usb2_phy_set_mode()
1943 tegra210_xusb_padctl_vbus_override(padctl, false); in tegra210_usb2_phy_set_mode()
1947 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_set_mode()
1956 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_on()
1957 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_on() local
1960 unsigned int index = lane->index; in tegra210_usb2_phy_power_on()
1964 port = tegra_xusb_find_usb2_port(padctl, index); in tegra210_usb2_phy_power_on()
1966 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index); in tegra210_usb2_phy_power_on()
1967 return -ENODEV; in tegra210_usb2_phy_power_on()
1970 priv = to_tegra210_xusb_padctl(padctl); in tegra210_usb2_phy_power_on()
1972 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_on()
1974 if (port->usb3_port_fake != -1) { in tegra210_usb2_phy_power_on()
1975 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_on()
1977 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1979 port->usb3_port_fake, index); in tegra210_usb2_phy_power_on()
1980 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_on()
1982 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1984 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1985 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1989 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1991 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1992 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1996 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1998 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1999 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
2002 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
2015 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
2017 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
2019 if (port->mode == USB_DR_MODE_UNKNOWN) in tegra210_usb2_phy_power_on()
2021 else if (port->mode == USB_DR_MODE_PERIPHERAL) in tegra210_usb2_phy_power_on()
2023 else if (port->mode == USB_DR_MODE_HOST) in tegra210_usb2_phy_power_on()
2025 else if (port->mode == USB_DR_MODE_OTG) in tegra210_usb2_phy_power_on()
2027 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
2029 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
2035 value |= (priv->fuse.hs_curr_level[index] + in tegra210_usb2_phy_power_on()
2036 usb2->hs_curr_level_offset) << in tegra210_usb2_phy_power_on()
2038 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
2040 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
2048 value |= (priv->fuse.hs_term_range_adj << in tegra210_usb2_phy_power_on()
2050 (priv->fuse.rpd_ctrl << in tegra210_usb2_phy_power_on()
2052 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
2054 value = padctl_readl(padctl, in tegra210_usb2_phy_power_on()
2058 if (port->mode == USB_DR_MODE_HOST) in tegra210_usb2_phy_power_on()
2064 padctl_writel(padctl, value, in tegra210_usb2_phy_power_on()
2067 if (pad->enable > 0) { in tegra210_usb2_phy_power_on()
2068 pad->enable++; in tegra210_usb2_phy_power_on()
2069 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
2073 err = clk_prepare_enable(pad->clk); in tegra210_usb2_phy_power_on()
2077 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
2086 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
2088 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
2090 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
2094 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
2096 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
2100 clk_disable_unprepare(pad->clk); in tegra210_usb2_phy_power_on()
2102 pad->enable++; in tegra210_usb2_phy_power_on()
2103 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
2108 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
2115 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_off()
2116 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_off() local
2120 port = tegra_xusb_find_usb2_port(padctl, lane->index); in tegra210_usb2_phy_power_off()
2122 dev_err(&phy->dev, "no port found for USB2 lane %u\n", in tegra210_usb2_phy_power_off()
2123 lane->index); in tegra210_usb2_phy_power_off()
2124 return -ENODEV; in tegra210_usb2_phy_power_off()
2127 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_off()
2129 if (port->usb3_port_fake != -1) { in tegra210_usb2_phy_power_off()
2130 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2132 port->usb3_port_fake); in tegra210_usb2_phy_power_off()
2133 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2137 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2139 port->usb3_port_fake); in tegra210_usb2_phy_power_off()
2140 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2144 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2146 port->usb3_port_fake); in tegra210_usb2_phy_power_off()
2147 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
2149 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_off()
2150 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake, in tegra210_usb2_phy_power_off()
2152 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_off()
2155 if (WARN_ON(pad->enable == 0)) in tegra210_usb2_phy_power_off()
2158 if (--pad->enable > 0) in tegra210_usb2_phy_power_off()
2161 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
2163 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
2166 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_off()
2180 tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_usb2_pad_probe() argument
2190 return ERR_PTR(-ENOMEM); in tegra210_usb2_pad_probe()
2192 pad = &usb2->base; in tegra210_usb2_pad_probe()
2193 pad->ops = &tegra210_usb2_lane_ops; in tegra210_usb2_pad_probe()
2194 pad->soc = soc; in tegra210_usb2_pad_probe()
2196 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_usb2_pad_probe()
2202 usb2->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_usb2_pad_probe()
2203 if (IS_ERR(usb2->clk)) { in tegra210_usb2_pad_probe()
2204 err = PTR_ERR(usb2->clk); in tegra210_usb2_pad_probe()
2205 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_usb2_pad_probe()
2213 dev_set_drvdata(&pad->dev, pad); in tegra210_usb2_pad_probe()
2218 device_unregister(&pad->dev); in tegra210_usb2_pad_probe()
2244 "xusb",
2248 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
2260 return ERR_PTR(-ENOMEM); in tegra210_hsic_lane_probe()
2262 INIT_LIST_HEAD(&hsic->base.list); in tegra210_hsic_lane_probe()
2263 hsic->base.soc = &pad->soc->lanes[index]; in tegra210_hsic_lane_probe()
2264 hsic->base.index = index; in tegra210_hsic_lane_probe()
2265 hsic->base.pad = pad; in tegra210_hsic_lane_probe()
2266 hsic->base.np = np; in tegra210_hsic_lane_probe()
2268 err = tegra_xusb_lane_parse_dt(&hsic->base, np); in tegra210_hsic_lane_probe()
2274 return &hsic->base; in tegra210_hsic_lane_probe()
2297 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_init() local
2300 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
2305 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
2319 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_on()
2320 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_on() local
2321 unsigned int index = lane->index; in tegra210_hsic_phy_power_on()
2325 err = regulator_enable(pad->supply); in tegra210_hsic_phy_power_on()
2329 padctl_writel(padctl, hsic->strobe_trim, in tegra210_hsic_phy_power_on()
2332 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
2335 value |= (hsic->tx_rtune_p << in tegra210_hsic_phy_power_on()
2337 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
2339 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
2344 value |= (hsic->rx_strobe_trim << in tegra210_hsic_phy_power_on()
2346 (hsic->rx_data_trim << in tegra210_hsic_phy_power_on()
2348 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
2350 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
2366 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
2368 err = clk_prepare_enable(pad->clk); in tegra210_hsic_phy_power_on()
2372 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
2381 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
2385 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
2387 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
2391 clk_disable_unprepare(pad->clk); in tegra210_hsic_phy_power_on()
2396 regulator_disable(pad->supply); in tegra210_hsic_phy_power_on()
2403 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_off()
2404 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_off() local
2405 unsigned int index = lane->index; in tegra210_hsic_phy_power_off()
2408 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_off()
2418 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_off()
2420 regulator_disable(pad->supply); in tegra210_hsic_phy_power_off()
2434 tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_hsic_pad_probe() argument
2444 return ERR_PTR(-ENOMEM); in tegra210_hsic_pad_probe()
2446 pad = &hsic->base; in tegra210_hsic_pad_probe()
2447 pad->ops = &tegra210_hsic_lane_ops; in tegra210_hsic_pad_probe()
2448 pad->soc = soc; in tegra210_hsic_pad_probe()
2450 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_hsic_pad_probe()
2456 hsic->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_hsic_pad_probe()
2457 if (IS_ERR(hsic->clk)) { in tegra210_hsic_pad_probe()
2458 err = PTR_ERR(hsic->clk); in tegra210_hsic_pad_probe()
2459 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_hsic_pad_probe()
2467 dev_set_drvdata(&pad->dev, pad); in tegra210_hsic_pad_probe()
2472 device_unregister(&pad->dev); in tegra210_hsic_pad_probe()
2498 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_uphy_lane_iddq_enable() local
2501 value = padctl_readl(padctl, lane->soc->regs.misc_ctl2); in tegra210_uphy_lane_iddq_enable()
2512 padctl_writel(padctl, value, lane->soc->regs.misc_ctl2); in tegra210_uphy_lane_iddq_enable()
2517 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_uphy_lane_iddq_disable() local
2520 value = padctl_readl(padctl, lane->soc->regs.misc_ctl2); in tegra210_uphy_lane_iddq_disable()
2531 padctl_writel(padctl, value, lane->soc->regs.misc_ctl2); in tegra210_uphy_lane_iddq_disable()
2546 "pcie-x1",
2547 "usb3-ss",
2549 "pcie-x4",
2553 TEGRA210_UPHY_LANE("pcie-0", 0x028, 12, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
2554 TEGRA210_UPHY_LANE("pcie-1", 0x028, 14, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(1)),
2555 TEGRA210_UPHY_LANE("pcie-2", 0x028, 16, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(2)),
2556 TEGRA210_UPHY_LANE("pcie-3", 0x028, 18, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(3)),
2557 TEGRA210_UPHY_LANE("pcie-4", 0x028, 20, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(4)),
2558 TEGRA210_UPHY_LANE("pcie-5", 0x028, 22, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(5)),
2559 TEGRA210_UPHY_LANE("pcie-6", 0x028, 24, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(6)),
2567 if (!lane || !lane->pad || !lane->pad->padctl) in tegra210_lane_to_usb3_port()
2574 return tegra_xusb_find_usb3_port(lane->pad->padctl, port); in tegra210_lane_to_usb3_port()
2579 struct device *dev = &phy->dev; in tegra210_usb3_phy_power_on()
2581 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_phy_power_on() local
2587 dev_err(dev, "no USB3 port found for lane %u\n", lane->index); in tegra210_usb3_phy_power_on()
2588 return -ENODEV; in tegra210_usb3_phy_power_on()
2591 index = usb3->base.index; in tegra210_usb3_phy_power_on()
2593 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_phy_power_on()
2595 if (!usb3->internal) in tegra210_usb3_phy_power_on()
2601 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); in tegra210_usb3_phy_power_on()
2602 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_phy_power_on()
2604 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_phy_power_on()
2609 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_phy_power_on()
2611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_phy_power_on()
2616 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_phy_power_on()
2618 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL, in tegra210_usb3_phy_power_on()
2621 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_phy_power_on()
2626 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_phy_power_on()
2628 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL, in tegra210_usb3_phy_power_on()
2631 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2633 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2637 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2639 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2643 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2645 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_on()
2652 struct device *dev = &phy->dev; in tegra210_usb3_phy_power_off()
2654 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_phy_power_off() local
2660 dev_err(dev, "no USB3 port found for lane %u\n", lane->index); in tegra210_usb3_phy_power_off()
2661 return -ENODEV; in tegra210_usb3_phy_power_off()
2664 index = usb3->base.index; in tegra210_usb3_phy_power_off()
2666 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2668 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2672 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2674 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2678 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2680 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_phy_power_off()
2693 return ERR_PTR(-ENOMEM); in tegra210_pcie_lane_probe()
2695 INIT_LIST_HEAD(&pcie->base.list); in tegra210_pcie_lane_probe()
2696 pcie->base.soc = &pad->soc->lanes[index]; in tegra210_pcie_lane_probe()
2697 pcie->base.index = index; in tegra210_pcie_lane_probe()
2698 pcie->base.pad = pad; in tegra210_pcie_lane_probe()
2699 pcie->base.np = np; in tegra210_pcie_lane_probe()
2701 err = tegra_xusb_lane_parse_dt(&pcie->base, np); in tegra210_pcie_lane_probe()
2707 return &pcie->base; in tegra210_pcie_lane_probe()
2732 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_init() local
2734 mutex_lock(&padctl->lock); in tegra210_pcie_phy_init()
2736 tegra210_uphy_init(padctl); in tegra210_pcie_phy_init()
2738 mutex_unlock(&padctl->lock); in tegra210_pcie_phy_init()
2746 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_on() local
2749 mutex_lock(&padctl->lock); in tegra210_pcie_phy_power_on()
2751 if (tegra_xusb_lane_check(lane, "usb3-ss")) in tegra210_pcie_phy_power_on()
2754 mutex_unlock(&padctl->lock); in tegra210_pcie_phy_power_on()
2761 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_off() local
2764 mutex_lock(&padctl->lock); in tegra210_pcie_phy_power_off()
2766 if (tegra_xusb_lane_check(lane, "usb3-ss")) in tegra210_pcie_phy_power_off()
2769 mutex_unlock(&padctl->lock); in tegra210_pcie_phy_power_off()
2781 tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_pcie_pad_probe() argument
2791 return ERR_PTR(-ENOMEM); in tegra210_pcie_pad_probe()
2793 pad = &pcie->base; in tegra210_pcie_pad_probe()
2794 pad->ops = &tegra210_pcie_lane_ops; in tegra210_pcie_pad_probe()
2795 pad->soc = soc; in tegra210_pcie_pad_probe()
2797 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_pcie_pad_probe()
2803 pcie->pll = devm_clk_get(&pad->dev, "pll"); in tegra210_pcie_pad_probe()
2804 if (IS_ERR(pcie->pll)) { in tegra210_pcie_pad_probe()
2805 err = PTR_ERR(pcie->pll); in tegra210_pcie_pad_probe()
2806 dev_err(&pad->dev, "failed to get PLL: %d\n", err); in tegra210_pcie_pad_probe()
2810 pcie->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_pcie_pad_probe()
2811 if (IS_ERR(pcie->rst)) { in tegra210_pcie_pad_probe()
2812 err = PTR_ERR(pcie->rst); in tegra210_pcie_pad_probe()
2813 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err); in tegra210_pcie_pad_probe()
2821 dev_set_drvdata(&pad->dev, pad); in tegra210_pcie_pad_probe()
2826 device_unregister(&pad->dev); in tegra210_pcie_pad_probe()
2851 TEGRA210_UPHY_LANE("sata-0", 0x028, 30, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2),
2863 return ERR_PTR(-ENOMEM); in tegra210_sata_lane_probe()
2865 INIT_LIST_HEAD(&sata->base.list); in tegra210_sata_lane_probe()
2866 sata->base.soc = &pad->soc->lanes[index]; in tegra210_sata_lane_probe()
2867 sata->base.index = index; in tegra210_sata_lane_probe()
2868 sata->base.pad = pad; in tegra210_sata_lane_probe()
2869 sata->base.np = np; in tegra210_sata_lane_probe()
2871 err = tegra_xusb_lane_parse_dt(&sata->base, np); in tegra210_sata_lane_probe()
2877 return &sata->base; in tegra210_sata_lane_probe()
2902 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_init() local
2904 mutex_lock(&padctl->lock); in tegra210_sata_phy_init()
2906 tegra210_uphy_init(padctl); in tegra210_sata_phy_init()
2908 mutex_unlock(&padctl->lock); in tegra210_sata_phy_init()
2915 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_on() local
2918 mutex_lock(&padctl->lock); in tegra210_sata_phy_power_on()
2920 if (tegra_xusb_lane_check(lane, "usb3-ss")) in tegra210_sata_phy_power_on()
2923 mutex_unlock(&padctl->lock); in tegra210_sata_phy_power_on()
2930 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_off() local
2933 mutex_lock(&padctl->lock); in tegra210_sata_phy_power_off()
2935 if (tegra_xusb_lane_check(lane, "usb3-ss")) in tegra210_sata_phy_power_off()
2938 mutex_unlock(&padctl->lock); in tegra210_sata_phy_power_off()
2950 tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_sata_pad_probe() argument
2960 return ERR_PTR(-ENOMEM); in tegra210_sata_pad_probe()
2962 pad = &sata->base; in tegra210_sata_pad_probe()
2963 pad->ops = &tegra210_sata_lane_ops; in tegra210_sata_pad_probe()
2964 pad->soc = soc; in tegra210_sata_pad_probe()
2966 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_sata_pad_probe()
2972 sata->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_sata_pad_probe()
2973 if (IS_ERR(sata->rst)) { in tegra210_sata_pad_probe()
2974 err = PTR_ERR(sata->rst); in tegra210_sata_pad_probe()
2975 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err); in tegra210_sata_pad_probe()
2983 dev_set_drvdata(&pad->dev, pad); in tegra210_sata_pad_probe()
2988 device_unregister(&pad->dev); in tegra210_sata_pad_probe()
3031 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); in tegra210_usb2_port_map()
3054 return tegra_xusb_find_lane(port->padctl, "hsic", port->index); in tegra210_hsic_port_map()
3076 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss"); in tegra210_usb3_port_map()
3089 struct tegra_xusb_padctl *padctl; in tegra210_utmi_port_reset() local
3094 padctl = lane->pad->padctl; in tegra210_utmi_port_reset()
3096 value = padctl_readl(padctl, in tegra210_utmi_port_reset()
3097 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane->index)); in tegra210_utmi_port_reset()
3101 tegra210_xusb_padctl_vbus_override(padctl, false); in tegra210_utmi_port_reset()
3102 tegra210_xusb_padctl_vbus_override(padctl, true); in tegra210_utmi_port_reset()
3120 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { in tegra210_xusb_read_fuse_calibration()
3121 fuse->hs_curr_level[i] = in tegra210_xusb_read_fuse_calibration()
3126 fuse->hs_term_range_adj = in tegra210_xusb_read_fuse_calibration()
3134 fuse->rpd_ctrl = in tegra210_xusb_read_fuse_calibration()
3145 struct tegra210_xusb_padctl *padctl; in tegra210_xusb_padctl_probe() local
3150 padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL); in tegra210_xusb_padctl_probe()
3151 if (!padctl) in tegra210_xusb_padctl_probe()
3152 return ERR_PTR(-ENOMEM); in tegra210_xusb_padctl_probe()
3154 padctl->base.dev = dev; in tegra210_xusb_padctl_probe()
3155 padctl->base.soc = soc; in tegra210_xusb_padctl_probe()
3157 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse); in tegra210_xusb_padctl_probe()
3161 np = of_parse_phandle(dev->of_node, "nvidia,pmc", 0); in tegra210_xusb_padctl_probe()
3174 return ERR_PTR(-EPROBE_DEFER); in tegra210_xusb_padctl_probe()
3176 padctl->regmap = dev_get_regmap(&pdev->dev, "usb_sleepwalk"); in tegra210_xusb_padctl_probe()
3177 if (!padctl->regmap) in tegra210_xusb_padctl_probe()
3181 return &padctl->base; in tegra210_xusb_padctl_probe()
3184 static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_remove() argument
3188 static void tegra210_xusb_padctl_save(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_save() argument
3190 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl); in tegra210_xusb_padctl_save()
3192 priv->context.usb2_pad_mux = in tegra210_xusb_padctl_save()
3193 padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_xusb_padctl_save()
3194 priv->context.usb2_port_cap = in tegra210_xusb_padctl_save()
3195 padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_xusb_padctl_save()
3196 priv->context.ss_port_map = in tegra210_xusb_padctl_save()
3197 padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_xusb_padctl_save()
3198 priv->context.usb3_pad_mux = in tegra210_xusb_padctl_save()
3199 padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_xusb_padctl_save()
3202 static void tegra210_xusb_padctl_restore(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_restore() argument
3204 struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl); in tegra210_xusb_padctl_restore()
3207 padctl_writel(padctl, priv->context.usb2_pad_mux, in tegra210_xusb_padctl_restore()
3209 padctl_writel(padctl, priv->context.usb2_port_cap, in tegra210_xusb_padctl_restore()
3211 padctl_writel(padctl, priv->context.ss_port_map, in tegra210_xusb_padctl_restore()
3214 list_for_each_entry(lane, &padctl->lanes, list) { in tegra210_xusb_padctl_restore()
3215 if (lane->pad->ops->iddq_enable) in tegra210_xusb_padctl_restore()
3219 padctl_writel(padctl, priv->context.usb3_pad_mux, in tegra210_xusb_padctl_restore()
3222 list_for_each_entry(lane, &padctl->lanes, list) { in tegra210_xusb_padctl_restore()
3223 if (lane->pad->ops->iddq_disable) in tegra210_xusb_padctl_restore()
3228 static int tegra210_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_suspend_noirq() argument
3230 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_suspend_noirq()
3232 tegra210_uphy_deinit(padctl); in tegra210_xusb_padctl_suspend_noirq()
3234 tegra210_xusb_padctl_save(padctl); in tegra210_xusb_padctl_suspend_noirq()
3236 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_suspend_noirq()
3240 static int tegra210_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_resume_noirq() argument
3242 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_resume_noirq()
3244 tegra210_xusb_padctl_restore(padctl); in tegra210_xusb_padctl_resume_noirq()
3246 tegra210_uphy_init(padctl); in tegra210_xusb_padctl_resume_noirq()
3248 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_resume_noirq()
3264 "avdd-pll-utmip",
3265 "avdd-pll-uerefe",
3266 "dvdd-pex-pll",
3267 "hvdd-pex-pll-e",
3295 MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver");