1 // SPDX-License-Identifier: GPL-2.0-only
21 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? 15 : 0)
22 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
24 #define FUSE_SKU_CALIB_HS_IREF_CAP_MASK 0x3
26 #define FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_MASK 0x3
28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
30 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
32 #define XUSB_PADCTL_USB2_PORT_CAP_PORT_CAP_MASK 0x3
33 #define XUSB_PADCTL_USB2_PORT_CAP_DISABLED 0x0
34 #define XUSB_PADCTL_USB2_PORT_CAP_HOST 0x1
35 #define XUSB_PADCTL_USB2_PORT_CAP_DEVICE 0x2
36 #define XUSB_PADCTL_USB2_PORT_CAP_OTG 0x3
38 #define XUSB_PADCTL_SS_PORT_MAP 0x014
41 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 4))
42 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
43 #define XUSB_PADCTL_SS_PORT_MAP_PORT_MAP_MASK 0x7
45 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
54 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
56 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
59 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
64 #define XUSB_PADCTL_IOPHY_USB3_PADX_CTL2(x) (0x058 + (x) * 4)
66 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_MASK 0xff
67 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_CDR_CNTL_VAL 0x24
69 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_Z_MASK 0x3f
71 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_G_MASK 0x3f
73 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_MASK 0xffff
74 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_EQ_VAL 0xf070
76 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_MASK 0xf
77 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2_RX_WANDER_VAL 0xf
79 #define XUSB_PADCTL_IOPHY_USB3_PADX_CTL4(x) (0x068 + (x) * 4)
81 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_TAP_MASK 0x1f
83 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_AMP_MASK 0x7f
84 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4_DFE_CNTL_VAL 0x002008ee
86 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \
87 					       0x0f8 + (x) * 4)
89 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_MASK 0x3
90 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL2_SPARE_IN_VAL 0x1
92 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \
93 					       0x11c + (x) * 4)
96 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \
97 					       0x128 + (x) * 4)
99 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_G_Z_MASK 0x3f
100 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_TAP_MASK 0x1f
101 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_AMP_MASK 0x7f
103 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_MASK 0xff
104 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_G_Z 0x21
105 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_TAP 0x32
106 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_AMP 0x33
107 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_CTLE_Z 0x48
108 #define XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_SEL_LATCH_G_Z 0xa1
110 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x0a0 + (x) * 4)
115 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_MASK 0x3
116 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(x) ((x) ? 0x0 : 0x3)
118 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_MASK 0x3f
119 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL 0x0e
120 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
121 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
123 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x0ac + (x) * 4)
125 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP_MASK 0x3
127 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0x7
130 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP (1 << 0)
132 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x0b8
135 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
136 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x5
137 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
138 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x3
140 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x0c0 + (x) * 4)
142 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWN_MASK 0x7
144 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RSLEWP_MASK 0x7
146 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEN_MASK 0x7
147 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEP_SHIFT 0
148 #define XUSB_PADCTL_HSIC_PAD_CTL0_TX_RTUNEP_MASK 0x7
150 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x0c8 + (x) * 4)
159 #define XUSB_PADCTL_HSIC_PAD_CTL1_AUTO_TERM_EN (1 << 0)
161 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x0d0 + (x) * 4)
163 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0x7
164 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
165 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0x7
167 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x0e0
168 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_STRB_TRIM_MASK 0x1f
170 #define XUSB_PADCTL_USB3_PAD_MUX 0x134
174 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
178 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL0_REFCLK_NDIV_MASK 0x3
181 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
183 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2 0x13c
185 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL1_CP_CNTL_MASK 0xf
187 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_PLL0_CP_CNTL_MASK 0xf
190 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_XDIGCLK_SEL_SHIFT 0
191 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2_XDIGCLK_SEL_MASK 0x7
193 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL3 0x140
196 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
198 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
200 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2 0x14c
202 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5 0x158
204 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6 0x15c
229 	mutex_lock(&padctl->lock);  in tegra124_xusb_padctl_enable()
231 	if (padctl->enable++ > 0)  in tegra124_xusb_padctl_enable()
251 	mutex_unlock(&padctl->lock);  in tegra124_xusb_padctl_enable()
252 	return 0;  in tegra124_xusb_padctl_enable()
259 	mutex_lock(&padctl->lock);  in tegra124_xusb_padctl_disable()
261 	if (WARN_ON(padctl->enable == 0))  in tegra124_xusb_padctl_disable()
264 	if (--padctl->enable > 0)  in tegra124_xusb_padctl_disable()
284 	mutex_unlock(&padctl->lock);  in tegra124_xusb_padctl_disable()
285 	return 0;  in tegra124_xusb_padctl_disable()
297 		return -ENODEV;  in tegra124_usb3_save_context()
299 	port->context_saved = true;  in tegra124_usb3_save_context()
300 	lane = port->base.lane;  in tegra124_usb3_save_context()
302 	if (lane->pad == padctl->pcie)  in tegra124_usb3_save_context()
303 		offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index);  in tegra124_usb3_save_context()
316 	port->tap1 = value & XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_TAP_MASK;  in tegra124_usb3_save_context()
327 	port->amp = value & XUSB_PADCTL_IOPHY_MISC_PAD_CTL6_MISC_OUT_AMP_MASK;  in tegra124_usb3_save_context()
334 	value |= (port->tap1 <<  in tegra124_usb3_save_context()
336 		 (port->amp <<  in tegra124_usb3_save_context()
356 	port->ctle_g = value &  in tegra124_usb3_save_context()
368 	port->ctle_z = value &  in tegra124_usb3_save_context()
376 	value |= (port->ctle_g <<  in tegra124_usb3_save_context()
378 		 (port->ctle_z <<  in tegra124_usb3_save_context()
382 	return 0;  in tegra124_usb3_save_context()
401 	return 0;  in tegra124_hsic_set_idle()
421 	TEGRA124_LANE("usb2-0", 0x004,  0, 0x3, usb2),
422 	TEGRA124_LANE("usb2-1", 0x004,  2, 0x3, usb2),
423 	TEGRA124_LANE("usb2-2", 0x004,  4, 0x3, usb2),
430 	struct tegra_xusb_usb2_lane *usb2;  in tegra124_usb2_lane_probe()  local
433 	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);  in tegra124_usb2_lane_probe()
434 	if (!usb2)  in tegra124_usb2_lane_probe()
435 		return ERR_PTR(-ENOMEM);  in tegra124_usb2_lane_probe()
437 	INIT_LIST_HEAD(&usb2->base.list);  in tegra124_usb2_lane_probe()
438 	usb2->base.soc = &pad->soc->lanes[index];  in tegra124_usb2_lane_probe()
439 	usb2->base.index = index;  in tegra124_usb2_lane_probe()
440 	usb2->base.pad = pad;  in tegra124_usb2_lane_probe()
441 	usb2->base.np = np;  in tegra124_usb2_lane_probe()
443 	err = tegra_xusb_lane_parse_dt(&usb2->base, np);  in tegra124_usb2_lane_probe()
444 	if (err < 0) {  in tegra124_usb2_lane_probe()
445 		kfree(usb2);  in tegra124_usb2_lane_probe()
449 	return &usb2->base;  in tegra124_usb2_lane_probe()
454 	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);  in tegra124_usb2_lane_remove()  local
456 	kfree(usb2);  in tegra124_usb2_lane_remove()
468 	return tegra124_xusb_padctl_enable(lane->pad->padctl);  in tegra124_usb2_phy_init()
475 	return tegra124_xusb_padctl_disable(lane->pad->padctl);  in tegra124_usb2_phy_exit()
481 	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);  in tegra124_usb2_phy_power_on()  local
482 	struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);  in tegra124_usb2_phy_power_on()
483 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra124_usb2_phy_power_on()
486 	unsigned int index = lane->index;  in tegra124_usb2_phy_power_on()
492 		dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);  in tegra124_usb2_phy_power_on()
493 		return -ENODEV;  in tegra124_usb2_phy_power_on()
503 	value |= (priv->fuse.hs_squelch_level <<  in tegra124_usb2_phy_power_on()
526 	value |= (priv->fuse.hs_curr_level[index] +  in tegra124_usb2_phy_power_on()
527 		  usb2->hs_curr_level_offset) <<  in tegra124_usb2_phy_power_on()
543 	value |= (priv->fuse.hs_term_range_adj <<  in tegra124_usb2_phy_power_on()
545 		 (priv->fuse.hs_iref_cap <<  in tegra124_usb2_phy_power_on()
549 	err = regulator_enable(port->supply);  in tegra124_usb2_phy_power_on()
553 	mutex_lock(&pad->lock);  in tegra124_usb2_phy_power_on()
555 	if (pad->enable++ > 0)  in tegra124_usb2_phy_power_on()
563 	mutex_unlock(&pad->lock);  in tegra124_usb2_phy_power_on()
564 	return 0;  in tegra124_usb2_phy_power_on()
570 	struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);  in tegra124_usb2_phy_power_off()
571 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra124_usb2_phy_power_off()
575 	port = tegra_xusb_find_usb2_port(padctl, lane->index);  in tegra124_usb2_phy_power_off()
577 		dev_err(&phy->dev, "no port found for USB2 lane %u\n",  in tegra124_usb2_phy_power_off()
578 			lane->index);  in tegra124_usb2_phy_power_off()
579 		return -ENODEV;  in tegra124_usb2_phy_power_off()
582 	mutex_lock(&pad->lock);  in tegra124_usb2_phy_power_off()
584 	if (WARN_ON(pad->enable == 0))  in tegra124_usb2_phy_power_off()
587 	if (--pad->enable > 0)  in tegra124_usb2_phy_power_off()
595 	regulator_disable(port->supply);  in tegra124_usb2_phy_power_off()
596 	mutex_unlock(&pad->lock);  in tegra124_usb2_phy_power_off()
597 	return 0;  in tegra124_usb2_phy_power_off()
613 	struct tegra_xusb_usb2_pad *usb2;  in tegra124_usb2_pad_probe()  local
617 	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);  in tegra124_usb2_pad_probe()
618 	if (!usb2)  in tegra124_usb2_pad_probe()
619 		return ERR_PTR(-ENOMEM);  in tegra124_usb2_pad_probe()
621 	mutex_init(&usb2->lock);  in tegra124_usb2_pad_probe()
623 	pad = &usb2->base;  in tegra124_usb2_pad_probe()
624 	pad->ops = &tegra124_usb2_lane_ops;  in tegra124_usb2_pad_probe()
625 	pad->soc = soc;  in tegra124_usb2_pad_probe()
628 	if (err < 0) {  in tegra124_usb2_pad_probe()
629 		kfree(usb2);  in tegra124_usb2_pad_probe()
634 	if (err < 0)  in tegra124_usb2_pad_probe()
637 	dev_set_drvdata(&pad->dev, pad);  in tegra124_usb2_pad_probe()
642 	device_unregister(&pad->dev);  in tegra124_usb2_pad_probe()
649 	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);  in tegra124_usb2_pad_remove()  local
651 	kfree(usb2);  in tegra124_usb2_pad_remove()
660 	.name = "usb2",
672 	TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, ulpi),
684 		return ERR_PTR(-ENOMEM);  in tegra124_ulpi_lane_probe()
686 	INIT_LIST_HEAD(&ulpi->base.list);  in tegra124_ulpi_lane_probe()
687 	ulpi->base.soc = &pad->soc->lanes[index];  in tegra124_ulpi_lane_probe()
688 	ulpi->base.index = index;  in tegra124_ulpi_lane_probe()
689 	ulpi->base.pad = pad;  in tegra124_ulpi_lane_probe()
690 	ulpi->base.np = np;  in tegra124_ulpi_lane_probe()
692 	err = tegra_xusb_lane_parse_dt(&ulpi->base, np);  in tegra124_ulpi_lane_probe()
693 	if (err < 0) {  in tegra124_ulpi_lane_probe()
698 	return &ulpi->base;  in tegra124_ulpi_lane_probe()
717 	return tegra124_xusb_padctl_enable(lane->pad->padctl);  in tegra124_ulpi_phy_init()
724 	return tegra124_xusb_padctl_disable(lane->pad->padctl);  in tegra124_ulpi_phy_exit()
729 	return 0;  in tegra124_ulpi_phy_power_on()
734 	return 0;  in tegra124_ulpi_phy_power_off()
756 		return ERR_PTR(-ENOMEM);  in tegra124_ulpi_pad_probe()
758 	pad = &ulpi->base;  in tegra124_ulpi_pad_probe()
759 	pad->ops = &tegra124_ulpi_lane_ops;  in tegra124_ulpi_pad_probe()
760 	pad->soc = soc;  in tegra124_ulpi_pad_probe()
763 	if (err < 0) {  in tegra124_ulpi_pad_probe()
769 	if (err < 0)  in tegra124_ulpi_pad_probe()
772 	dev_set_drvdata(&pad->dev, pad);  in tegra124_ulpi_pad_probe()
777 	device_unregister(&pad->dev);  in tegra124_ulpi_pad_probe()
807 	TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, hsic),
808 	TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, hsic),
820 		return ERR_PTR(-ENOMEM);  in tegra124_hsic_lane_probe()
822 	INIT_LIST_HEAD(&hsic->base.list);  in tegra124_hsic_lane_probe()
823 	hsic->base.soc = &pad->soc->lanes[index];  in tegra124_hsic_lane_probe()
824 	hsic->base.index = index;  in tegra124_hsic_lane_probe()
825 	hsic->base.pad = pad;  in tegra124_hsic_lane_probe()
826 	hsic->base.np = np;  in tegra124_hsic_lane_probe()
828 	err = tegra_xusb_lane_parse_dt(&hsic->base, np);  in tegra124_hsic_lane_probe()
829 	if (err < 0) {  in tegra124_hsic_lane_probe()
834 	return &hsic->base;  in tegra124_hsic_lane_probe()
853 	return tegra124_xusb_padctl_enable(lane->pad->padctl);  in tegra124_hsic_phy_init()
860 	return tegra124_xusb_padctl_disable(lane->pad->padctl);  in tegra124_hsic_phy_exit()
867 	struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);  in tegra124_hsic_phy_power_on()
868 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra124_hsic_phy_power_on()
869 	unsigned int index = lane->index;  in tegra124_hsic_phy_power_on()
873 	err = regulator_enable(pad->supply);  in tegra124_hsic_phy_power_on()
877 	padctl_writel(padctl, hsic->strobe_trim,  in tegra124_hsic_phy_power_on()
882 	if (hsic->auto_term)  in tegra124_hsic_phy_power_on()
898 	value |= (hsic->tx_rtune_n <<  in tegra124_hsic_phy_power_on()
900 		(hsic->tx_rtune_p <<  in tegra124_hsic_phy_power_on()
902 		(hsic->tx_rslew_n <<  in tegra124_hsic_phy_power_on()
904 		(hsic->tx_rslew_p <<  in tegra124_hsic_phy_power_on()
913 	value |= (hsic->rx_strobe_trim <<  in tegra124_hsic_phy_power_on()
915 		(hsic->rx_data_trim <<  in tegra124_hsic_phy_power_on()
930 	return 0;  in tegra124_hsic_phy_power_on()
936 	struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);  in tegra124_hsic_phy_power_off()
937 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra124_hsic_phy_power_off()
938 	unsigned int index = lane->index;  in tegra124_hsic_phy_power_off()
948 	regulator_disable(pad->supply);  in tegra124_hsic_phy_power_off()
950 	return 0;  in tegra124_hsic_phy_power_off()
972 		return ERR_PTR(-ENOMEM);  in tegra124_hsic_pad_probe()
974 	pad = &hsic->base;  in tegra124_hsic_pad_probe()
975 	pad->ops = &tegra124_hsic_lane_ops;  in tegra124_hsic_pad_probe()
976 	pad->soc = soc;  in tegra124_hsic_pad_probe()
979 	if (err < 0) {  in tegra124_hsic_pad_probe()
985 	if (err < 0)  in tegra124_hsic_pad_probe()
988 	dev_set_drvdata(&pad->dev, pad);  in tegra124_hsic_pad_probe()
993 	device_unregister(&pad->dev);  in tegra124_hsic_pad_probe()
1019 	"usb3-ss",
1024 	TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, pcie),
1025 	TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, pcie),
1026 	TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, pcie),
1027 	TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, pcie),
1028 	TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, pcie),
1040 		return ERR_PTR(-ENOMEM);  in tegra124_pcie_lane_probe()
1042 	INIT_LIST_HEAD(&pcie->base.list);  in tegra124_pcie_lane_probe()
1043 	pcie->base.soc = &pad->soc->lanes[index];  in tegra124_pcie_lane_probe()
1044 	pcie->base.index = index;  in tegra124_pcie_lane_probe()
1045 	pcie->base.pad = pad;  in tegra124_pcie_lane_probe()
1046 	pcie->base.np = np;  in tegra124_pcie_lane_probe()
1048 	err = tegra_xusb_lane_parse_dt(&pcie->base, np);  in tegra124_pcie_lane_probe()
1049 	if (err < 0) {  in tegra124_pcie_lane_probe()
1054 	return &pcie->base;  in tegra124_pcie_lane_probe()
1073 	return tegra124_xusb_padctl_enable(lane->pad->padctl);  in tegra124_pcie_phy_init()
1080 	return tegra124_xusb_padctl_disable(lane->pad->padctl);  in tegra124_pcie_phy_exit()
1086 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra124_pcie_phy_power_on()
1088 	int err = -ETIMEDOUT;  in tegra124_pcie_phy_power_on()
1110 			err = 0;  in tegra124_pcie_phy_power_on()
1118 	value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);  in tegra124_pcie_phy_power_on()
1127 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra124_pcie_phy_power_off()
1131 	value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);  in tegra124_pcie_phy_power_off()
1138 	return 0;  in tegra124_pcie_phy_power_off()
1160 		return ERR_PTR(-ENOMEM);  in tegra124_pcie_pad_probe()
1162 	pad = &pcie->base;  in tegra124_pcie_pad_probe()
1163 	pad->ops = &tegra124_pcie_lane_ops;  in tegra124_pcie_pad_probe()
1164 	pad->soc = soc;  in tegra124_pcie_pad_probe()
1167 	if (err < 0) {  in tegra124_pcie_pad_probe()
1173 	if (err < 0)  in tegra124_pcie_pad_probe()
1176 	dev_set_drvdata(&pad->dev, pad);  in tegra124_pcie_pad_probe()
1181 	device_unregister(&pad->dev);  in tegra124_pcie_pad_probe()
1206 	TEGRA124_LANE("sata-0", 0x134, 26, 0x3, pcie),
1218 		return ERR_PTR(-ENOMEM);  in tegra124_sata_lane_probe()
1220 	INIT_LIST_HEAD(&sata->base.list);  in tegra124_sata_lane_probe()
1221 	sata->base.soc = &pad->soc->lanes[index];  in tegra124_sata_lane_probe()
1222 	sata->base.index = index;  in tegra124_sata_lane_probe()
1223 	sata->base.pad = pad;  in tegra124_sata_lane_probe()
1224 	sata->base.np = np;  in tegra124_sata_lane_probe()
1226 	err = tegra_xusb_lane_parse_dt(&sata->base, np);  in tegra124_sata_lane_probe()
1227 	if (err < 0) {  in tegra124_sata_lane_probe()
1232 	return &sata->base;  in tegra124_sata_lane_probe()
1251 	return tegra124_xusb_padctl_enable(lane->pad->padctl);  in tegra124_sata_phy_init()
1258 	return tegra124_xusb_padctl_disable(lane->pad->padctl);  in tegra124_sata_phy_exit()
1264 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra124_sata_phy_power_on()
1266 	int err = -ETIMEDOUT;  in tegra124_sata_phy_power_on()
1292 			err = 0;  in tegra124_sata_phy_power_on()
1300 	value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);  in tegra124_sata_phy_power_on()
1309 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;  in tegra124_sata_phy_power_off()
1313 	value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);  in tegra124_sata_phy_power_off()
1334 	return 0;  in tegra124_sata_phy_power_off()
1356 		return ERR_PTR(-ENOMEM);  in tegra124_sata_pad_probe()
1358 	pad = &sata->base;  in tegra124_sata_pad_probe()
1359 	pad->ops = &tegra124_sata_lane_ops;  in tegra124_sata_pad_probe()
1360 	pad->soc = soc;  in tegra124_sata_pad_probe()
1363 	if (err < 0) {  in tegra124_sata_pad_probe()
1369 	if (err < 0)  in tegra124_sata_pad_probe()
1372 	dev_set_drvdata(&pad->dev, pad);  in tegra124_sata_pad_probe()
1377 	device_unregister(&pad->dev);  in tegra124_sata_pad_probe()
1411 	return 0;  in tegra124_usb2_port_enable()
1421 	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);  in tegra124_usb2_port_map()
1434 	return 0;  in tegra124_ulpi_port_enable()
1444 	return tegra_xusb_find_lane(port->padctl, "ulpi", port->index);  in tegra124_ulpi_port_map()
1456 	return 0;  in tegra124_hsic_port_enable()
1466 	return tegra_xusb_find_lane(port->padctl, "hsic", port->index);  in tegra124_hsic_port_map()
1479 	struct tegra_xusb_padctl *padctl = port->padctl;  in tegra124_usb3_port_enable()
1480 	struct tegra_xusb_lane *lane = usb3->base.lane;  in tegra124_usb3_port_enable()
1481 	unsigned int index = port->index, offset;  in tegra124_usb3_port_enable()
1486 	if (!usb3->internal)  in tegra124_usb3_port_enable()
1492 	value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);  in tegra124_usb3_port_enable()
1496 	 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks  in tegra124_usb3_port_enable()
1514 	if (usb3->context_saved) {  in tegra124_usb3_port_enable()
1519 		value |= (usb3->ctle_g <<  in tegra124_usb3_port_enable()
1521 			 (usb3->ctle_z <<  in tegra124_usb3_port_enable()
1529 	if (usb3->context_saved) {  in tegra124_usb3_port_enable()
1534 		value |= (usb3->tap1 <<  in tegra124_usb3_port_enable()
1536 			 (usb3->amp <<  in tegra124_usb3_port_enable()
1542 	if (lane->pad == padctl->pcie)  in tegra124_usb3_port_enable()
1543 		offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(lane->index);  in tegra124_usb3_port_enable()
1554 	if (lane->pad == padctl->pcie)  in tegra124_usb3_port_enable()
1555 		offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(lane->index);  in tegra124_usb3_port_enable()
1564 	if (lane->pad == padctl->sata) {  in tegra124_usb3_port_enable()
1568 		value |= 0x2 <<  in tegra124_usb3_port_enable()
1580 		value |= (0x7 <<  in tegra124_usb3_port_enable()
1582 			 (0x8 <<  in tegra124_usb3_port_enable()
1584 			 (0x8 <<  in tegra124_usb3_port_enable()
1610 	return 0;  in tegra124_usb3_port_enable()
1615 	struct tegra_xusb_padctl *padctl = port->padctl;  in tegra124_usb3_port_disable()
1619 	value |= XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN_EARLY(port->index);  in tegra124_usb3_port_disable()
1625 	value |= XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(port->index);  in tegra124_usb3_port_disable()
1631 	value |= XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(port->index);  in tegra124_usb3_port_disable()
1635 	value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(port->index);  in tegra124_usb3_port_disable()
1636 	value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->index, 0x7);  in tegra124_usb3_port_disable()
1641 	{ 0, "pcie", 0 },
1643 	{ 1, "sata", 0 },
1644 	{ 0, NULL,   0 },
1650 	return tegra_xusb_port_find_lane(port, tegra124_usb3_map, "usb3-ss");  in tegra124_usb3_port_map()
1669 	if (err < 0)  in tegra124_xusb_read_fuse_calibration()
1672 	for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) {  in tegra124_xusb_read_fuse_calibration()
1673 		fuse->hs_curr_level[i] =  in tegra124_xusb_read_fuse_calibration()
1677 	fuse->hs_iref_cap =  in tegra124_xusb_read_fuse_calibration()
1680 	fuse->hs_term_range_adj =  in tegra124_xusb_read_fuse_calibration()
1683 	fuse->hs_squelch_level =  in tegra124_xusb_read_fuse_calibration()
1687 	return 0;  in tegra124_xusb_read_fuse_calibration()
1699 		return ERR_PTR(-ENOMEM);  in tegra124_xusb_padctl_probe()
1701 	padctl->base.dev = dev;  in tegra124_xusb_padctl_probe()
1702 	padctl->base.soc = soc;  in tegra124_xusb_padctl_probe()
1704 	err = tegra124_xusb_read_fuse_calibration(&padctl->fuse);  in tegra124_xusb_padctl_probe()
1705 	if (err < 0)  in tegra124_xusb_padctl_probe()
1708 	return &padctl->base;  in tegra124_xusb_padctl_probe()
1723 	"avdd-pll-utmip",
1724 	"avdd-pll-erefe",
1725 	"avdd-pex-pll",
1726 	"hvdd-pex-pll-e",
1733 		.usb2 = {