Lines Matching +full:rk3568 +full:- +full:pcie3 +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
21 /* Register for RK3568 */
55 struct phy *phy; member
66 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
68 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rockchip_p3phy_set_mode()
73 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode()
76 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode()
79 dev_err(&phy->dev, "%s, invalid mode\n", __func__); in rockchip_p3phy_set_mode()
80 return -EINVAL; in rockchip_p3phy_set_mode()
88 struct phy *phy = priv->phy; in rockchip_p3phy_rk3568_init() local
94 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM); in rockchip_p3phy_rk3568_init()
96 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3568_init()
97 dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); in rockchip_p3phy_rk3568_init()
98 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3568_init()
104 dev_info(&phy->dev, "bifurcation enabled\n"); in rockchip_p3phy_rk3568_init()
105 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, in rockchip_p3phy_rk3568_init()
107 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, in rockchip_p3phy_rk3568_init()
110 dev_dbg(&phy->dev, "bifurcation disabled\n"); in rockchip_p3phy_rk3568_init()
111 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, in rockchip_p3phy_rk3568_init()
115 reset_control_deassert(priv->p30phy); in rockchip_p3phy_rk3568_init()
117 ret = regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3568_init()
122 dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", in rockchip_p3phy_rk3568_init()
138 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); in rockchip_p3phy_rk3588_init()
141 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3588_init()
142 if (!priv->lanes[i]) in rockchip_p3phy_rk3588_init()
145 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3588_init()
159 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); in rockchip_p3phy_rk3588_init()
162 if (!IS_ERR(priv->pipe_grf)) { in rockchip_p3phy_rk3588_init()
165 regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, in rockchip_p3phy_rk3588_init()
169 reset_control_deassert(priv->p30phy); in rockchip_p3phy_rk3588_init()
171 ret = regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3588_init()
175 ret |= regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3588_init()
180 dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n", in rockchip_p3phy_rk3588_init()
189 static int rochchip_p3phy_init(struct phy *phy) in rochchip_p3phy_init() argument
191 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rochchip_p3phy_init()
194 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); in rochchip_p3phy_init()
196 dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret); in rochchip_p3phy_init()
200 reset_control_assert(priv->p30phy); in rochchip_p3phy_init()
203 if (priv->ops->phy_init) { in rochchip_p3phy_init()
204 ret = priv->ops->phy_init(priv); in rochchip_p3phy_init()
206 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rochchip_p3phy_init()
212 static int rochchip_p3phy_exit(struct phy *phy) in rochchip_p3phy_exit() argument
214 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); in rochchip_p3phy_exit()
216 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); in rochchip_p3phy_exit()
217 reset_control_assert(priv->p30phy); in rochchip_p3phy_exit()
231 struct device *dev = &pdev->dev; in rockchip_p3phy_probe()
233 struct device_node *np = dev->of_node; in rockchip_p3phy_probe()
238 return -ENOMEM; in rockchip_p3phy_probe()
240 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in rockchip_p3phy_probe()
241 if (IS_ERR(priv->mmio)) { in rockchip_p3phy_probe()
242 ret = PTR_ERR(priv->mmio); in rockchip_p3phy_probe()
246 priv->ops = of_device_get_match_data(&pdev->dev); in rockchip_p3phy_probe()
247 if (!priv->ops) { in rockchip_p3phy_probe()
249 return -EINVAL; in rockchip_p3phy_probe()
252 priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); in rockchip_p3phy_probe()
253 if (IS_ERR(priv->phy_grf)) { in rockchip_p3phy_probe()
255 return PTR_ERR(priv->phy_grf); in rockchip_p3phy_probe()
258 if (of_device_is_compatible(np, "rockchip,rk3588-pcie3-phy")) { in rockchip_p3phy_probe()
259 priv->pipe_grf = in rockchip_p3phy_probe()
260 syscon_regmap_lookup_by_phandle(dev->of_node, in rockchip_p3phy_probe()
261 "rockchip,pipe-grf"); in rockchip_p3phy_probe()
262 if (IS_ERR(priv->pipe_grf)) in rockchip_p3phy_probe()
265 priv->pipe_grf = NULL; in rockchip_p3phy_probe()
268 priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", in rockchip_p3phy_probe()
269 priv->lanes, 2, in rockchip_p3phy_probe()
270 ARRAY_SIZE(priv->lanes)); in rockchip_p3phy_probe()
272 /* if no data-lanes assume aggregation */ in rockchip_p3phy_probe()
273 if (priv->num_lanes == -EINVAL) { in rockchip_p3phy_probe()
274 dev_dbg(dev, "no data-lanes property found\n"); in rockchip_p3phy_probe()
275 priv->num_lanes = 1; in rockchip_p3phy_probe()
276 priv->lanes[0] = 1; in rockchip_p3phy_probe()
277 } else if (priv->num_lanes < 0) { in rockchip_p3phy_probe()
278 dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes); in rockchip_p3phy_probe()
279 return priv->num_lanes; in rockchip_p3phy_probe()
282 priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); in rockchip_p3phy_probe()
283 if (IS_ERR(priv->phy)) { in rockchip_p3phy_probe()
285 return PTR_ERR(priv->phy); in rockchip_p3phy_probe()
288 priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); in rockchip_p3phy_probe()
289 if (IS_ERR(priv->p30phy)) { in rockchip_p3phy_probe()
290 return dev_err_probe(dev, PTR_ERR(priv->p30phy), in rockchip_p3phy_probe()
291 "failed to get phy reset control\n"); in rockchip_p3phy_probe()
293 if (!priv->p30phy) in rockchip_p3phy_probe()
294 dev_info(dev, "no phy reset control specified\n"); in rockchip_p3phy_probe()
296 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); in rockchip_p3phy_probe()
297 if (priv->num_clks < 1) in rockchip_p3phy_probe()
298 return -ENODEV; in rockchip_p3phy_probe()
301 phy_set_drvdata(priv->phy, priv); in rockchip_p3phy_probe()
307 { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
308 { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
316 .name = "rockchip-snps-pcie3-phy",
321 MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");